1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2 or later, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program. If not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/boards.h" 29 #include "hw/loader.h" 30 #include "hw/sysbus.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/spike.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/char/riscv_htif.h" 37 #include "hw/intc/riscv_aclint.h" 38 #include "chardev/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 42 #include <libfdt.h> 43 44 static const MemMapEntry spike_memmap[] = { 45 [SPIKE_MROM] = { 0x1000, 0xf000 }, 46 [SPIKE_HTIF] = { 0x1000000, 0x1000 }, 47 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 48 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 49 }; 50 51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 52 bool is_32_bit, bool htif_custom_base) 53 { 54 void *fdt; 55 int fdt_size; 56 uint64_t addr, size; 57 unsigned long clint_addr; 58 int cpu, socket; 59 MachineState *ms = MACHINE(s); 60 uint32_t *clint_cells; 61 uint32_t cpu_phandle, intc_phandle, phandle = 1; 62 char *mem_name, *clint_name, *clust_name; 63 char *core_name, *cpu_name, *intc_name; 64 static const char * const clint_compat[2] = { 65 "sifive,clint0", "riscv,clint0" 66 }; 67 68 fdt = ms->fdt = create_device_tree(&fdt_size); 69 if (!fdt) { 70 error_report("create_device_tree() failed"); 71 exit(1); 72 } 73 74 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 75 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 77 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 78 79 qemu_fdt_add_subnode(fdt, "/htif"); 80 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 81 if (htif_custom_base) { 82 qemu_fdt_setprop_cells(fdt, "/htif", "reg", 83 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); 84 } 85 86 qemu_fdt_add_subnode(fdt, "/soc"); 87 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 88 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 89 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 90 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 91 92 qemu_fdt_add_subnode(fdt, "/cpus"); 93 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 94 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 95 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 96 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 97 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 98 99 for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { 100 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 101 qemu_fdt_add_subnode(fdt, clust_name); 102 103 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 104 105 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 106 cpu_phandle = phandle++; 107 108 cpu_name = g_strdup_printf("/cpus/cpu@%d", 109 s->soc[socket].hartid_base + cpu); 110 qemu_fdt_add_subnode(fdt, cpu_name); 111 if (is_32_bit) { 112 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 113 } else { 114 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 115 } 116 riscv_isa_write_fdt(&s->soc[socket].harts[cpu], fdt, cpu_name); 117 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 118 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 119 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 120 s->soc[socket].hartid_base + cpu); 121 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 122 riscv_socket_fdt_write_id(ms, cpu_name, socket); 123 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 124 125 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 126 qemu_fdt_add_subnode(fdt, intc_name); 127 intc_phandle = phandle++; 128 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 129 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 130 "riscv,cpu-intc"); 131 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 132 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 133 134 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 135 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 136 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 137 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 138 139 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 140 qemu_fdt_add_subnode(fdt, core_name); 141 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 142 143 g_free(core_name); 144 g_free(intc_name); 145 g_free(cpu_name); 146 } 147 148 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); 149 size = riscv_socket_mem_size(ms, socket); 150 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 151 qemu_fdt_add_subnode(fdt, mem_name); 152 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 153 addr >> 32, addr, size >> 32, size); 154 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 155 riscv_socket_fdt_write_id(ms, mem_name, socket); 156 g_free(mem_name); 157 158 clint_addr = memmap[SPIKE_CLINT].base + 159 (memmap[SPIKE_CLINT].size * socket); 160 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 161 qemu_fdt_add_subnode(fdt, clint_name); 162 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", 163 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 164 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 165 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); 166 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 167 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 168 riscv_socket_fdt_write_id(ms, clint_name, socket); 169 170 g_free(clint_name); 171 g_free(clint_cells); 172 g_free(clust_name); 173 } 174 175 riscv_socket_fdt_write_distance_matrix(ms); 176 177 qemu_fdt_add_subnode(fdt, "/chosen"); 178 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 179 } 180 181 static bool spike_test_elf_image(char *filename) 182 { 183 Error *err = NULL; 184 185 load_elf_hdr(filename, NULL, NULL, &err); 186 if (err) { 187 error_free(err); 188 return false; 189 } else { 190 return true; 191 } 192 } 193 194 static void spike_board_init(MachineState *machine) 195 { 196 const MemMapEntry *memmap = spike_memmap; 197 SpikeState *s = SPIKE_MACHINE(machine); 198 MemoryRegion *system_memory = get_system_memory(); 199 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 200 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base; 201 hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base; 202 target_ulong kernel_start_addr; 203 char *firmware_name; 204 uint32_t fdt_load_addr; 205 uint64_t kernel_entry; 206 char *soc_name; 207 int i, base_hartid, hart_count; 208 bool htif_custom_base = false; 209 210 /* Check socket count limit */ 211 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { 212 error_report("number of sockets/nodes should be less than %d", 213 SPIKE_SOCKETS_MAX); 214 exit(1); 215 } 216 217 /* Initialize sockets */ 218 for (i = 0; i < riscv_socket_count(machine); i++) { 219 if (!riscv_socket_check_hartids(machine, i)) { 220 error_report("discontinuous hartids in socket%d", i); 221 exit(1); 222 } 223 224 base_hartid = riscv_socket_first_hartid(machine, i); 225 if (base_hartid < 0) { 226 error_report("can't find hartid base for socket%d", i); 227 exit(1); 228 } 229 230 hart_count = riscv_socket_hart_count(machine, i); 231 if (hart_count < 0) { 232 error_report("can't find hart count for socket%d", i); 233 exit(1); 234 } 235 236 soc_name = g_strdup_printf("soc%d", i); 237 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 238 TYPE_RISCV_HART_ARRAY); 239 g_free(soc_name); 240 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 241 machine->cpu_type, &error_abort); 242 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 243 base_hartid, &error_abort); 244 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 245 hart_count, &error_abort); 246 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 247 248 /* Core Local Interruptor (timer and IPI) for each socket */ 249 riscv_aclint_swi_create( 250 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, 251 base_hartid, hart_count, false); 252 riscv_aclint_mtimer_create( 253 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + 254 RISCV_ACLINT_SWI_SIZE, 255 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 256 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 257 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); 258 } 259 260 /* register system main memory (actual RAM) */ 261 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 262 machine->ram); 263 264 /* boot rom */ 265 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 266 memmap[SPIKE_MROM].size, &error_fatal); 267 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 268 mask_rom); 269 270 /* Find firmware */ 271 firmware_name = riscv_find_firmware(machine->firmware, 272 riscv_default_firmware_name(&s->soc[0])); 273 274 /* 275 * Test the given firmware or kernel file to see if it is an ELF image. 276 * If it is an ELF, we assume it contains the symbols required for 277 * the HTIF console, otherwise we fall back to use the custom base 278 * passed from device tree for the HTIF console. 279 */ 280 if (!firmware_name && !machine->kernel_filename) { 281 htif_custom_base = true; 282 } else { 283 if (firmware_name) { 284 htif_custom_base = !spike_test_elf_image(firmware_name); 285 } 286 if (!htif_custom_base && machine->kernel_filename) { 287 htif_custom_base = !spike_test_elf_image(machine->kernel_filename); 288 } 289 } 290 291 /* Load firmware */ 292 if (firmware_name) { 293 firmware_end_addr = riscv_load_firmware(firmware_name, 294 &firmware_load_addr, 295 htif_symbol_callback); 296 g_free(firmware_name); 297 } 298 299 /* Create device tree */ 300 create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); 301 302 /* Load kernel */ 303 if (machine->kernel_filename) { 304 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 305 firmware_end_addr); 306 307 kernel_entry = riscv_load_kernel(machine, &s->soc[0], 308 kernel_start_addr, 309 true, htif_symbol_callback); 310 } else { 311 /* 312 * If dynamic firmware is used, it doesn't know where is the next mode 313 * if kernel argument is not set. 314 */ 315 kernel_entry = 0; 316 } 317 318 fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, 319 memmap[SPIKE_DRAM].size, 320 machine); 321 riscv_load_fdt(fdt_load_addr, machine->fdt); 322 323 /* load the reset vector */ 324 riscv_setup_rom_reset_vec(machine, &s->soc[0], firmware_load_addr, 325 memmap[SPIKE_MROM].base, 326 memmap[SPIKE_MROM].size, kernel_entry, 327 fdt_load_addr); 328 329 /* initialize HTIF using symbols found in load_kernel */ 330 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base, 331 htif_custom_base); 332 } 333 334 static void spike_set_signature(Object *obj, const char *val, Error **errp) 335 { 336 sig_file = g_strdup(val); 337 } 338 339 static void spike_machine_instance_init(Object *obj) 340 { 341 } 342 343 static void spike_machine_class_init(ObjectClass *oc, void *data) 344 { 345 MachineClass *mc = MACHINE_CLASS(oc); 346 347 mc->desc = "RISC-V Spike board"; 348 mc->init = spike_board_init; 349 mc->max_cpus = SPIKE_CPUS_MAX; 350 mc->is_default = true; 351 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 352 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 353 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 354 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 355 mc->numa_mem_supported = true; 356 /* platform instead of architectural choice */ 357 mc->cpu_cluster_has_numa_boundary = true; 358 mc->default_ram_id = "riscv.spike.ram"; 359 object_class_property_add_str(oc, "signature", NULL, spike_set_signature); 360 object_class_property_set_description(oc, "signature", 361 "File to write ACT test signature"); 362 object_class_property_add_uint8_ptr(oc, "signature-granularity", 363 &line_size, OBJ_PROP_FLAG_WRITE); 364 object_class_property_set_description(oc, "signature-granularity", 365 "Size of each line in ACT signature " 366 "file"); 367 } 368 369 static const TypeInfo spike_machine_typeinfo = { 370 .name = MACHINE_TYPE_NAME("spike"), 371 .parent = TYPE_MACHINE, 372 .class_init = spike_machine_class_init, 373 .instance_init = spike_machine_instance_init, 374 .instance_size = sizeof(SpikeState), 375 }; 376 377 static void spike_machine_init_register_types(void) 378 { 379 type_register_static(&spike_machine_typeinfo); 380 } 381 382 type_init(spike_machine_init_register_types) 383