1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2 or later, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program. If not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/boards.h" 29 #include "hw/loader.h" 30 #include "hw/sysbus.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/spike.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/char/riscv_htif.h" 37 #include "hw/intc/riscv_aclint.h" 38 #include "chardev/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 42 #include <libfdt.h> 43 44 static const MemMapEntry spike_memmap[] = { 45 [SPIKE_MROM] = { 0x1000, 0xf000 }, 46 [SPIKE_HTIF] = { 0x1000000, 0x1000 }, 47 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 48 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 49 }; 50 51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 52 uint64_t mem_size, const char *cmdline, 53 bool is_32_bit, bool htif_custom_base) 54 { 55 void *fdt; 56 int fdt_size; 57 uint64_t addr, size; 58 unsigned long clint_addr; 59 int cpu, socket; 60 MachineState *mc = MACHINE(s); 61 uint32_t *clint_cells; 62 uint32_t cpu_phandle, intc_phandle, phandle = 1; 63 char *name, *mem_name, *clint_name, *clust_name; 64 char *core_name, *cpu_name, *intc_name; 65 static const char * const clint_compat[2] = { 66 "sifive,clint0", "riscv,clint0" 67 }; 68 69 fdt = mc->fdt = create_device_tree(&fdt_size); 70 if (!fdt) { 71 error_report("create_device_tree() failed"); 72 exit(1); 73 } 74 75 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 76 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 77 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 78 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 79 80 qemu_fdt_add_subnode(fdt, "/htif"); 81 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 82 if (htif_custom_base) { 83 qemu_fdt_setprop_cells(fdt, "/htif", "reg", 84 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); 85 } 86 87 qemu_fdt_add_subnode(fdt, "/soc"); 88 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 89 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 90 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 91 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 92 93 qemu_fdt_add_subnode(fdt, "/cpus"); 94 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 95 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 96 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 97 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 98 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 99 100 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 101 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 102 qemu_fdt_add_subnode(fdt, clust_name); 103 104 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 105 106 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 107 cpu_phandle = phandle++; 108 109 cpu_name = g_strdup_printf("/cpus/cpu@%d", 110 s->soc[socket].hartid_base + cpu); 111 qemu_fdt_add_subnode(fdt, cpu_name); 112 if (is_32_bit) { 113 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 114 } else { 115 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 116 } 117 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 118 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 119 g_free(name); 120 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 121 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 122 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 123 s->soc[socket].hartid_base + cpu); 124 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 125 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 126 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 127 128 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 129 qemu_fdt_add_subnode(fdt, intc_name); 130 intc_phandle = phandle++; 131 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 132 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 133 "riscv,cpu-intc"); 134 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 135 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 136 137 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 138 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 139 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 140 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 141 142 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 143 qemu_fdt_add_subnode(fdt, core_name); 144 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 145 146 g_free(core_name); 147 g_free(intc_name); 148 g_free(cpu_name); 149 } 150 151 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); 152 size = riscv_socket_mem_size(mc, socket); 153 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 154 qemu_fdt_add_subnode(fdt, mem_name); 155 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 156 addr >> 32, addr, size >> 32, size); 157 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 158 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 159 g_free(mem_name); 160 161 clint_addr = memmap[SPIKE_CLINT].base + 162 (memmap[SPIKE_CLINT].size * socket); 163 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 164 qemu_fdt_add_subnode(fdt, clint_name); 165 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", 166 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 167 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 168 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); 169 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 170 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 171 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 172 173 g_free(clint_name); 174 g_free(clint_cells); 175 g_free(clust_name); 176 } 177 178 riscv_socket_fdt_write_distance_matrix(mc, fdt); 179 180 qemu_fdt_add_subnode(fdt, "/chosen"); 181 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 182 183 if (cmdline && *cmdline) { 184 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 185 } 186 } 187 188 static bool spike_test_elf_image(char *filename) 189 { 190 Error *err = NULL; 191 192 load_elf_hdr(filename, NULL, NULL, &err); 193 if (err) { 194 error_free(err); 195 return false; 196 } else { 197 return true; 198 } 199 } 200 201 static void spike_board_init(MachineState *machine) 202 { 203 const MemMapEntry *memmap = spike_memmap; 204 SpikeState *s = SPIKE_MACHINE(machine); 205 MemoryRegion *system_memory = get_system_memory(); 206 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 207 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base; 208 target_ulong kernel_start_addr; 209 char *firmware_name; 210 uint32_t fdt_load_addr; 211 uint64_t kernel_entry; 212 char *soc_name; 213 int i, base_hartid, hart_count; 214 bool htif_custom_base = false; 215 216 /* Check socket count limit */ 217 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { 218 error_report("number of sockets/nodes should be less than %d", 219 SPIKE_SOCKETS_MAX); 220 exit(1); 221 } 222 223 /* Initialize sockets */ 224 for (i = 0; i < riscv_socket_count(machine); i++) { 225 if (!riscv_socket_check_hartids(machine, i)) { 226 error_report("discontinuous hartids in socket%d", i); 227 exit(1); 228 } 229 230 base_hartid = riscv_socket_first_hartid(machine, i); 231 if (base_hartid < 0) { 232 error_report("can't find hartid base for socket%d", i); 233 exit(1); 234 } 235 236 hart_count = riscv_socket_hart_count(machine, i); 237 if (hart_count < 0) { 238 error_report("can't find hart count for socket%d", i); 239 exit(1); 240 } 241 242 soc_name = g_strdup_printf("soc%d", i); 243 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 244 TYPE_RISCV_HART_ARRAY); 245 g_free(soc_name); 246 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 247 machine->cpu_type, &error_abort); 248 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 249 base_hartid, &error_abort); 250 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 251 hart_count, &error_abort); 252 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 253 254 /* Core Local Interruptor (timer and IPI) for each socket */ 255 riscv_aclint_swi_create( 256 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, 257 base_hartid, hart_count, false); 258 riscv_aclint_mtimer_create( 259 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + 260 RISCV_ACLINT_SWI_SIZE, 261 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 262 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 263 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); 264 } 265 266 /* register system main memory (actual RAM) */ 267 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 268 machine->ram); 269 270 /* boot rom */ 271 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 272 memmap[SPIKE_MROM].size, &error_fatal); 273 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 274 mask_rom); 275 276 /* Find firmware */ 277 firmware_name = riscv_find_firmware(machine->firmware, 278 riscv_default_firmware_name(&s->soc[0])); 279 280 /* 281 * Test the given firmware or kernel file to see if it is an ELF image. 282 * If it is an ELF, we assume it contains the symbols required for 283 * the HTIF console, otherwise we fall back to use the custom base 284 * passed from device tree for the HTIF console. 285 */ 286 if (!firmware_name && !machine->kernel_filename) { 287 htif_custom_base = true; 288 } else { 289 if (firmware_name) { 290 htif_custom_base = !spike_test_elf_image(firmware_name); 291 } 292 if (!htif_custom_base && machine->kernel_filename) { 293 htif_custom_base = !spike_test_elf_image(machine->kernel_filename); 294 } 295 } 296 297 /* Load firmware */ 298 if (firmware_name) { 299 firmware_end_addr = riscv_load_firmware(firmware_name, 300 memmap[SPIKE_DRAM].base, 301 htif_symbol_callback); 302 g_free(firmware_name); 303 } 304 305 /* Create device tree */ 306 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 307 riscv_is_32bit(&s->soc[0]), htif_custom_base); 308 309 /* Load kernel */ 310 if (machine->kernel_filename) { 311 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 312 firmware_end_addr); 313 314 kernel_entry = riscv_load_kernel(machine->kernel_filename, 315 kernel_start_addr, 316 htif_symbol_callback); 317 318 if (machine->initrd_filename) { 319 hwaddr start; 320 hwaddr end = riscv_load_initrd(machine->initrd_filename, 321 machine->ram_size, kernel_entry, 322 &start); 323 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 324 "linux,initrd-start", start); 325 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 326 end); 327 } 328 } else { 329 /* 330 * If dynamic firmware is used, it doesn't know where is the next mode 331 * if kernel argument is not set. 332 */ 333 kernel_entry = 0; 334 } 335 336 /* Compute the fdt load address in dram */ 337 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, 338 machine->ram_size, machine->fdt); 339 340 /* load the reset vector */ 341 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, 342 memmap[SPIKE_MROM].base, 343 memmap[SPIKE_MROM].size, kernel_entry, 344 fdt_load_addr); 345 346 /* initialize HTIF using symbols found in load_kernel */ 347 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base, 348 htif_custom_base); 349 } 350 351 static void spike_machine_instance_init(Object *obj) 352 { 353 } 354 355 static void spike_machine_class_init(ObjectClass *oc, void *data) 356 { 357 MachineClass *mc = MACHINE_CLASS(oc); 358 359 mc->desc = "RISC-V Spike board"; 360 mc->init = spike_board_init; 361 mc->max_cpus = SPIKE_CPUS_MAX; 362 mc->is_default = true; 363 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 364 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 365 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 366 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 367 mc->numa_mem_supported = true; 368 mc->default_ram_id = "riscv.spike.ram"; 369 } 370 371 static const TypeInfo spike_machine_typeinfo = { 372 .name = MACHINE_TYPE_NAME("spike"), 373 .parent = TYPE_MACHINE, 374 .class_init = spike_machine_class_init, 375 .instance_init = spike_machine_instance_init, 376 .instance_size = sizeof(SpikeState), 377 }; 378 379 static void spike_machine_init_register_types(void) 380 { 381 type_register_static(&spike_machine_typeinfo); 382 } 383 384 type_init(spike_machine_init_register_types) 385