1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/boards.h" 30 #include "hw/loader.h" 31 #include "hw/sysbus.h" 32 #include "target/riscv/cpu.h" 33 #include "hw/riscv/riscv_hart.h" 34 #include "hw/riscv/spike.h" 35 #include "hw/riscv/boot.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/char/riscv_htif.h" 38 #include "hw/intc/sifive_clint.h" 39 #include "chardev/char.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/sysemu.h" 42 43 static const MemMapEntry spike_memmap[] = { 44 [SPIKE_MROM] = { 0x1000, 0xf000 }, 45 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 46 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 47 }; 48 49 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 50 uint64_t mem_size, const char *cmdline, bool is_32_bit) 51 { 52 void *fdt; 53 uint64_t addr, size; 54 unsigned long clint_addr; 55 int cpu, socket; 56 MachineState *mc = MACHINE(s); 57 uint32_t *clint_cells; 58 uint32_t cpu_phandle, intc_phandle, phandle = 1; 59 char *name, *mem_name, *clint_name, *clust_name; 60 char *core_name, *cpu_name, *intc_name; 61 static const char * const clint_compat[2] = { 62 "sifive,clint0", "riscv,clint0" 63 }; 64 65 fdt = s->fdt = create_device_tree(&s->fdt_size); 66 if (!fdt) { 67 error_report("create_device_tree() failed"); 68 exit(1); 69 } 70 71 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 72 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 73 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 74 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 75 76 qemu_fdt_add_subnode(fdt, "/htif"); 77 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 78 79 qemu_fdt_add_subnode(fdt, "/soc"); 80 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 81 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 82 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 83 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 84 85 qemu_fdt_add_subnode(fdt, "/cpus"); 86 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 87 SIFIVE_CLINT_TIMEBASE_FREQ); 88 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 89 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 90 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 91 92 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 93 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 94 qemu_fdt_add_subnode(fdt, clust_name); 95 96 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 97 98 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 99 cpu_phandle = phandle++; 100 101 cpu_name = g_strdup_printf("/cpus/cpu@%d", 102 s->soc[socket].hartid_base + cpu); 103 qemu_fdt_add_subnode(fdt, cpu_name); 104 if (is_32_bit) { 105 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 106 } else { 107 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 108 } 109 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 110 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 111 g_free(name); 112 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 113 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 114 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 115 s->soc[socket].hartid_base + cpu); 116 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 117 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 118 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 119 120 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 121 qemu_fdt_add_subnode(fdt, intc_name); 122 intc_phandle = phandle++; 123 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 124 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 125 "riscv,cpu-intc"); 126 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 127 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 128 129 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 130 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 131 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 132 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 133 134 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 135 qemu_fdt_add_subnode(fdt, core_name); 136 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 137 138 g_free(core_name); 139 g_free(intc_name); 140 g_free(cpu_name); 141 } 142 143 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); 144 size = riscv_socket_mem_size(mc, socket); 145 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 146 qemu_fdt_add_subnode(fdt, mem_name); 147 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 148 addr >> 32, addr, size >> 32, size); 149 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 150 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 151 g_free(mem_name); 152 153 clint_addr = memmap[SPIKE_CLINT].base + 154 (memmap[SPIKE_CLINT].size * socket); 155 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 156 qemu_fdt_add_subnode(fdt, clint_name); 157 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", 158 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 159 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 160 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); 161 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 162 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 163 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 164 165 g_free(clint_name); 166 g_free(clint_cells); 167 g_free(clust_name); 168 } 169 170 riscv_socket_fdt_write_distance_matrix(mc, fdt); 171 172 if (cmdline) { 173 qemu_fdt_add_subnode(fdt, "/chosen"); 174 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 175 } 176 } 177 178 static void spike_board_init(MachineState *machine) 179 { 180 const MemMapEntry *memmap = spike_memmap; 181 SpikeState *s = SPIKE_MACHINE(machine); 182 MemoryRegion *system_memory = get_system_memory(); 183 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 184 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 185 target_ulong firmware_end_addr, kernel_start_addr; 186 uint32_t fdt_load_addr; 187 uint64_t kernel_entry; 188 char *soc_name; 189 int i, base_hartid, hart_count; 190 191 /* Check socket count limit */ 192 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { 193 error_report("number of sockets/nodes should be less than %d", 194 SPIKE_SOCKETS_MAX); 195 exit(1); 196 } 197 198 /* Initialize sockets */ 199 for (i = 0; i < riscv_socket_count(machine); i++) { 200 if (!riscv_socket_check_hartids(machine, i)) { 201 error_report("discontinuous hartids in socket%d", i); 202 exit(1); 203 } 204 205 base_hartid = riscv_socket_first_hartid(machine, i); 206 if (base_hartid < 0) { 207 error_report("can't find hartid base for socket%d", i); 208 exit(1); 209 } 210 211 hart_count = riscv_socket_hart_count(machine, i); 212 if (hart_count < 0) { 213 error_report("can't find hart count for socket%d", i); 214 exit(1); 215 } 216 217 soc_name = g_strdup_printf("soc%d", i); 218 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 219 TYPE_RISCV_HART_ARRAY); 220 g_free(soc_name); 221 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 222 machine->cpu_type, &error_abort); 223 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 224 base_hartid, &error_abort); 225 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 226 hart_count, &error_abort); 227 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 228 229 /* Core Local Interruptor (timer and IPI) for each socket */ 230 sifive_clint_create( 231 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, 232 memmap[SPIKE_CLINT].size, base_hartid, hart_count, 233 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 234 SIFIVE_CLINT_TIMEBASE_FREQ, false); 235 } 236 237 /* register system main memory (actual RAM) */ 238 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 239 machine->ram_size, &error_fatal); 240 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 241 main_mem); 242 243 /* create device tree */ 244 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 245 riscv_is_32bit(&s->soc[0])); 246 247 /* boot rom */ 248 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 249 memmap[SPIKE_MROM].size, &error_fatal); 250 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 251 mask_rom); 252 253 /* 254 * Not like other RISC-V machines that use plain binary bios images, 255 * keeping ELF files here was intentional because BIN files don't work 256 * for the Spike machine as HTIF emulation depends on ELF parsing. 257 */ 258 if (riscv_is_32bit(&s->soc[0])) { 259 firmware_end_addr = riscv_find_and_load_firmware(machine, 260 RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base, 261 htif_symbol_callback); 262 } else { 263 firmware_end_addr = riscv_find_and_load_firmware(machine, 264 RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base, 265 htif_symbol_callback); 266 } 267 268 if (machine->kernel_filename) { 269 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 270 firmware_end_addr); 271 272 kernel_entry = riscv_load_kernel(machine->kernel_filename, 273 kernel_start_addr, 274 htif_symbol_callback); 275 276 if (machine->initrd_filename) { 277 hwaddr start; 278 hwaddr end = riscv_load_initrd(machine->initrd_filename, 279 machine->ram_size, kernel_entry, 280 &start); 281 qemu_fdt_setprop_cell(s->fdt, "/chosen", 282 "linux,initrd-start", start); 283 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 284 end); 285 } 286 } else { 287 /* 288 * If dynamic firmware is used, it doesn't know where is the next mode 289 * if kernel argument is not set. 290 */ 291 kernel_entry = 0; 292 } 293 294 /* Compute the fdt load address in dram */ 295 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, 296 machine->ram_size, s->fdt); 297 /* load the reset vector */ 298 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, 299 memmap[SPIKE_MROM].base, 300 memmap[SPIKE_MROM].size, kernel_entry, 301 fdt_load_addr, s->fdt); 302 303 /* initialize HTIF using symbols found in load_kernel */ 304 htif_mm_init(system_memory, mask_rom, 305 &s->soc[0].harts[0].env, serial_hd(0)); 306 } 307 308 static void spike_machine_instance_init(Object *obj) 309 { 310 } 311 312 static void spike_machine_class_init(ObjectClass *oc, void *data) 313 { 314 MachineClass *mc = MACHINE_CLASS(oc); 315 316 mc->desc = "RISC-V Spike board"; 317 mc->init = spike_board_init; 318 mc->max_cpus = SPIKE_CPUS_MAX; 319 mc->is_default = true; 320 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 321 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 322 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 323 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 324 mc->numa_mem_supported = true; 325 } 326 327 static const TypeInfo spike_machine_typeinfo = { 328 .name = MACHINE_TYPE_NAME("spike"), 329 .parent = TYPE_MACHINE, 330 .class_init = spike_machine_class_init, 331 .instance_init = spike_machine_instance_init, 332 .instance_size = sizeof(SpikeState), 333 }; 334 335 static void spike_machine_init_register_types(void) 336 { 337 type_register_static(&spike_machine_typeinfo); 338 } 339 340 type_init(spike_machine_init_register_types) 341