1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/boards.h" 30 #include "hw/loader.h" 31 #include "hw/sysbus.h" 32 #include "target/riscv/cpu.h" 33 #include "hw/riscv/riscv_hart.h" 34 #include "hw/riscv/spike.h" 35 #include "hw/riscv/boot.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/char/riscv_htif.h" 38 #include "hw/intc/riscv_aclint.h" 39 #include "chardev/char.h" 40 #include "sysemu/device_tree.h" 41 #include "sysemu/sysemu.h" 42 43 static const MemMapEntry spike_memmap[] = { 44 [SPIKE_MROM] = { 0x1000, 0xf000 }, 45 [SPIKE_HTIF] = { 0x1000000, 0x1000 }, 46 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 47 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 48 }; 49 50 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 51 uint64_t mem_size, const char *cmdline, bool is_32_bit) 52 { 53 void *fdt; 54 uint64_t addr, size; 55 unsigned long clint_addr; 56 int cpu, socket; 57 MachineState *mc = MACHINE(s); 58 uint32_t *clint_cells; 59 uint32_t cpu_phandle, intc_phandle, phandle = 1; 60 char *name, *mem_name, *clint_name, *clust_name; 61 char *core_name, *cpu_name, *intc_name; 62 static const char * const clint_compat[2] = { 63 "sifive,clint0", "riscv,clint0" 64 }; 65 66 fdt = s->fdt = create_device_tree(&s->fdt_size); 67 if (!fdt) { 68 error_report("create_device_tree() failed"); 69 exit(1); 70 } 71 72 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 73 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 74 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 75 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 76 77 qemu_fdt_add_subnode(fdt, "/htif"); 78 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 79 if (!htif_uses_elf_symbols()) { 80 qemu_fdt_setprop_cells(fdt, "/htif", "reg", 81 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); 82 } 83 84 qemu_fdt_add_subnode(fdt, "/soc"); 85 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 86 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 87 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 88 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 89 90 qemu_fdt_add_subnode(fdt, "/cpus"); 91 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 92 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 93 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 94 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 95 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 96 97 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 98 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 99 qemu_fdt_add_subnode(fdt, clust_name); 100 101 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 102 103 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 104 cpu_phandle = phandle++; 105 106 cpu_name = g_strdup_printf("/cpus/cpu@%d", 107 s->soc[socket].hartid_base + cpu); 108 qemu_fdt_add_subnode(fdt, cpu_name); 109 if (is_32_bit) { 110 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 111 } else { 112 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 113 } 114 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 115 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 116 g_free(name); 117 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 118 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 119 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 120 s->soc[socket].hartid_base + cpu); 121 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 122 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 123 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 124 125 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 126 qemu_fdt_add_subnode(fdt, intc_name); 127 intc_phandle = phandle++; 128 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 129 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 130 "riscv,cpu-intc"); 131 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 132 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 133 134 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 135 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 136 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 137 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 138 139 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 140 qemu_fdt_add_subnode(fdt, core_name); 141 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 142 143 g_free(core_name); 144 g_free(intc_name); 145 g_free(cpu_name); 146 } 147 148 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); 149 size = riscv_socket_mem_size(mc, socket); 150 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 151 qemu_fdt_add_subnode(fdt, mem_name); 152 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 153 addr >> 32, addr, size >> 32, size); 154 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 155 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 156 g_free(mem_name); 157 158 clint_addr = memmap[SPIKE_CLINT].base + 159 (memmap[SPIKE_CLINT].size * socket); 160 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 161 qemu_fdt_add_subnode(fdt, clint_name); 162 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", 163 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 164 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 165 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); 166 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 167 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 168 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 169 170 g_free(clint_name); 171 g_free(clint_cells); 172 g_free(clust_name); 173 } 174 175 riscv_socket_fdt_write_distance_matrix(mc, fdt); 176 177 qemu_fdt_add_subnode(fdt, "/chosen"); 178 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 179 180 if (cmdline && *cmdline) { 181 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 182 } 183 } 184 185 static void spike_board_init(MachineState *machine) 186 { 187 const MemMapEntry *memmap = spike_memmap; 188 SpikeState *s = SPIKE_MACHINE(machine); 189 MemoryRegion *system_memory = get_system_memory(); 190 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 191 target_ulong firmware_end_addr, kernel_start_addr; 192 uint32_t fdt_load_addr; 193 uint64_t kernel_entry; 194 char *soc_name; 195 int i, base_hartid, hart_count; 196 197 /* Check socket count limit */ 198 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { 199 error_report("number of sockets/nodes should be less than %d", 200 SPIKE_SOCKETS_MAX); 201 exit(1); 202 } 203 204 /* Initialize sockets */ 205 for (i = 0; i < riscv_socket_count(machine); i++) { 206 if (!riscv_socket_check_hartids(machine, i)) { 207 error_report("discontinuous hartids in socket%d", i); 208 exit(1); 209 } 210 211 base_hartid = riscv_socket_first_hartid(machine, i); 212 if (base_hartid < 0) { 213 error_report("can't find hartid base for socket%d", i); 214 exit(1); 215 } 216 217 hart_count = riscv_socket_hart_count(machine, i); 218 if (hart_count < 0) { 219 error_report("can't find hart count for socket%d", i); 220 exit(1); 221 } 222 223 soc_name = g_strdup_printf("soc%d", i); 224 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 225 TYPE_RISCV_HART_ARRAY); 226 g_free(soc_name); 227 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 228 machine->cpu_type, &error_abort); 229 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 230 base_hartid, &error_abort); 231 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 232 hart_count, &error_abort); 233 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 234 235 /* Core Local Interruptor (timer and IPI) for each socket */ 236 riscv_aclint_swi_create( 237 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, 238 base_hartid, hart_count, false); 239 riscv_aclint_mtimer_create( 240 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + 241 RISCV_ACLINT_SWI_SIZE, 242 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 243 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 244 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); 245 } 246 247 /* register system main memory (actual RAM) */ 248 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 249 machine->ram); 250 251 /* boot rom */ 252 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 253 memmap[SPIKE_MROM].size, &error_fatal); 254 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 255 mask_rom); 256 257 /* 258 * Not like other RISC-V machines that use plain binary bios images, 259 * keeping ELF files here was intentional because BIN files don't work 260 * for the Spike machine as HTIF emulation depends on ELF parsing. 261 */ 262 if (riscv_is_32bit(&s->soc[0])) { 263 firmware_end_addr = riscv_find_and_load_firmware(machine, 264 RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, 265 htif_symbol_callback); 266 } else { 267 firmware_end_addr = riscv_find_and_load_firmware(machine, 268 RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, 269 htif_symbol_callback); 270 } 271 272 /* Load kernel */ 273 if (machine->kernel_filename) { 274 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 275 firmware_end_addr); 276 277 kernel_entry = riscv_load_kernel(machine->kernel_filename, 278 kernel_start_addr, 279 htif_symbol_callback); 280 } else { 281 /* 282 * If dynamic firmware is used, it doesn't know where is the next mode 283 * if kernel argument is not set. 284 */ 285 kernel_entry = 0; 286 } 287 288 /* Create device tree */ 289 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 290 riscv_is_32bit(&s->soc[0])); 291 292 /* Load initrd */ 293 if (machine->kernel_filename && machine->initrd_filename) { 294 hwaddr start; 295 hwaddr end = riscv_load_initrd(machine->initrd_filename, 296 machine->ram_size, kernel_entry, 297 &start); 298 qemu_fdt_setprop_cell(s->fdt, "/chosen", 299 "linux,initrd-start", start); 300 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 301 end); 302 } 303 304 /* Compute the fdt load address in dram */ 305 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, 306 machine->ram_size, s->fdt); 307 /* load the reset vector */ 308 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, 309 memmap[SPIKE_MROM].base, 310 memmap[SPIKE_MROM].size, kernel_entry, 311 fdt_load_addr, s->fdt); 312 313 /* initialize HTIF using symbols found in load_kernel */ 314 htif_mm_init(system_memory, mask_rom, 315 &s->soc[0].harts[0].env, serial_hd(0), 316 memmap[SPIKE_HTIF].base); 317 } 318 319 static void spike_machine_instance_init(Object *obj) 320 { 321 } 322 323 static void spike_machine_class_init(ObjectClass *oc, void *data) 324 { 325 MachineClass *mc = MACHINE_CLASS(oc); 326 327 mc->desc = "RISC-V Spike board"; 328 mc->init = spike_board_init; 329 mc->max_cpus = SPIKE_CPUS_MAX; 330 mc->is_default = true; 331 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 332 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 333 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 334 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 335 mc->numa_mem_supported = true; 336 mc->default_ram_id = "riscv.spike.ram"; 337 } 338 339 static const TypeInfo spike_machine_typeinfo = { 340 .name = MACHINE_TYPE_NAME("spike"), 341 .parent = TYPE_MACHINE, 342 .class_init = spike_machine_class_init, 343 .instance_init = spike_machine_instance_init, 344 .instance_size = sizeof(SpikeState), 345 }; 346 347 static void spike_machine_init_register_types(void) 348 { 349 type_register_static(&spike_machine_typeinfo); 350 } 351 352 type_init(spike_machine_init_register_types) 353