1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2 or later, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program. If not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/boards.h" 29 #include "hw/loader.h" 30 #include "hw/sysbus.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/spike.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/char/riscv_htif.h" 37 #include "hw/intc/riscv_aclint.h" 38 #include "chardev/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 42 #include <libfdt.h> 43 44 static const MemMapEntry spike_memmap[] = { 45 [SPIKE_MROM] = { 0x1000, 0xf000 }, 46 [SPIKE_HTIF] = { 0x1000000, 0x1000 }, 47 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 48 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 49 }; 50 51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 52 bool is_32_bit, bool htif_custom_base) 53 { 54 void *fdt; 55 int fdt_size; 56 uint64_t addr, size; 57 unsigned long clint_addr; 58 int cpu, socket; 59 MachineState *ms = MACHINE(s); 60 uint32_t *clint_cells; 61 uint32_t cpu_phandle, intc_phandle, phandle = 1; 62 char *name, *mem_name, *clint_name, *clust_name; 63 char *core_name, *cpu_name, *intc_name; 64 static const char * const clint_compat[2] = { 65 "sifive,clint0", "riscv,clint0" 66 }; 67 68 fdt = ms->fdt = create_device_tree(&fdt_size); 69 if (!fdt) { 70 error_report("create_device_tree() failed"); 71 exit(1); 72 } 73 74 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 75 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 77 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 78 79 qemu_fdt_add_subnode(fdt, "/htif"); 80 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 81 if (htif_custom_base) { 82 qemu_fdt_setprop_cells(fdt, "/htif", "reg", 83 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); 84 } 85 86 qemu_fdt_add_subnode(fdt, "/soc"); 87 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 88 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 89 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 90 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 91 92 qemu_fdt_add_subnode(fdt, "/cpus"); 93 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 94 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 95 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 96 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 97 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 98 99 for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { 100 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 101 qemu_fdt_add_subnode(fdt, clust_name); 102 103 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 104 105 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 106 cpu_phandle = phandle++; 107 108 cpu_name = g_strdup_printf("/cpus/cpu@%d", 109 s->soc[socket].hartid_base + cpu); 110 qemu_fdt_add_subnode(fdt, cpu_name); 111 if (is_32_bit) { 112 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 113 } else { 114 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 115 } 116 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 117 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 118 g_free(name); 119 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 120 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 121 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 122 s->soc[socket].hartid_base + cpu); 123 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 124 riscv_socket_fdt_write_id(ms, cpu_name, socket); 125 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 126 127 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 128 qemu_fdt_add_subnode(fdt, intc_name); 129 intc_phandle = phandle++; 130 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 131 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 132 "riscv,cpu-intc"); 133 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 134 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 135 136 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 137 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 138 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 139 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 140 141 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 142 qemu_fdt_add_subnode(fdt, core_name); 143 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 144 145 g_free(core_name); 146 g_free(intc_name); 147 g_free(cpu_name); 148 } 149 150 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); 151 size = riscv_socket_mem_size(ms, socket); 152 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 153 qemu_fdt_add_subnode(fdt, mem_name); 154 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 155 addr >> 32, addr, size >> 32, size); 156 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 157 riscv_socket_fdt_write_id(ms, mem_name, socket); 158 g_free(mem_name); 159 160 clint_addr = memmap[SPIKE_CLINT].base + 161 (memmap[SPIKE_CLINT].size * socket); 162 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 163 qemu_fdt_add_subnode(fdt, clint_name); 164 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", 165 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 166 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 167 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); 168 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 169 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 170 riscv_socket_fdt_write_id(ms, clint_name, socket); 171 172 g_free(clint_name); 173 g_free(clint_cells); 174 g_free(clust_name); 175 } 176 177 riscv_socket_fdt_write_distance_matrix(ms); 178 179 qemu_fdt_add_subnode(fdt, "/chosen"); 180 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 181 } 182 183 static bool spike_test_elf_image(char *filename) 184 { 185 Error *err = NULL; 186 187 load_elf_hdr(filename, NULL, NULL, &err); 188 if (err) { 189 error_free(err); 190 return false; 191 } else { 192 return true; 193 } 194 } 195 196 static void spike_board_init(MachineState *machine) 197 { 198 const MemMapEntry *memmap = spike_memmap; 199 SpikeState *s = SPIKE_MACHINE(machine); 200 MemoryRegion *system_memory = get_system_memory(); 201 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 202 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base; 203 target_ulong kernel_start_addr; 204 char *firmware_name; 205 uint32_t fdt_load_addr; 206 uint64_t kernel_entry; 207 char *soc_name; 208 int i, base_hartid, hart_count; 209 bool htif_custom_base = false; 210 211 /* Check socket count limit */ 212 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { 213 error_report("number of sockets/nodes should be less than %d", 214 SPIKE_SOCKETS_MAX); 215 exit(1); 216 } 217 218 /* Initialize sockets */ 219 for (i = 0; i < riscv_socket_count(machine); i++) { 220 if (!riscv_socket_check_hartids(machine, i)) { 221 error_report("discontinuous hartids in socket%d", i); 222 exit(1); 223 } 224 225 base_hartid = riscv_socket_first_hartid(machine, i); 226 if (base_hartid < 0) { 227 error_report("can't find hartid base for socket%d", i); 228 exit(1); 229 } 230 231 hart_count = riscv_socket_hart_count(machine, i); 232 if (hart_count < 0) { 233 error_report("can't find hart count for socket%d", i); 234 exit(1); 235 } 236 237 soc_name = g_strdup_printf("soc%d", i); 238 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 239 TYPE_RISCV_HART_ARRAY); 240 g_free(soc_name); 241 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 242 machine->cpu_type, &error_abort); 243 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 244 base_hartid, &error_abort); 245 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 246 hart_count, &error_abort); 247 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 248 249 /* Core Local Interruptor (timer and IPI) for each socket */ 250 riscv_aclint_swi_create( 251 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, 252 base_hartid, hart_count, false); 253 riscv_aclint_mtimer_create( 254 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + 255 RISCV_ACLINT_SWI_SIZE, 256 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 257 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 258 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); 259 } 260 261 /* register system main memory (actual RAM) */ 262 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 263 machine->ram); 264 265 /* boot rom */ 266 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 267 memmap[SPIKE_MROM].size, &error_fatal); 268 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 269 mask_rom); 270 271 /* Find firmware */ 272 firmware_name = riscv_find_firmware(machine->firmware, 273 riscv_default_firmware_name(&s->soc[0])); 274 275 /* 276 * Test the given firmware or kernel file to see if it is an ELF image. 277 * If it is an ELF, we assume it contains the symbols required for 278 * the HTIF console, otherwise we fall back to use the custom base 279 * passed from device tree for the HTIF console. 280 */ 281 if (!firmware_name && !machine->kernel_filename) { 282 htif_custom_base = true; 283 } else { 284 if (firmware_name) { 285 htif_custom_base = !spike_test_elf_image(firmware_name); 286 } 287 if (!htif_custom_base && machine->kernel_filename) { 288 htif_custom_base = !spike_test_elf_image(machine->kernel_filename); 289 } 290 } 291 292 /* Load firmware */ 293 if (firmware_name) { 294 firmware_end_addr = riscv_load_firmware(firmware_name, 295 memmap[SPIKE_DRAM].base, 296 htif_symbol_callback); 297 g_free(firmware_name); 298 } 299 300 /* Create device tree */ 301 create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); 302 303 /* Load kernel */ 304 if (machine->kernel_filename) { 305 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 306 firmware_end_addr); 307 308 kernel_entry = riscv_load_kernel(machine, kernel_start_addr, 309 htif_symbol_callback); 310 311 if (machine->initrd_filename) { 312 riscv_load_initrd(machine, kernel_entry); 313 } 314 315 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 316 qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", 317 machine->kernel_cmdline); 318 } 319 } else { 320 /* 321 * If dynamic firmware is used, it doesn't know where is the next mode 322 * if kernel argument is not set. 323 */ 324 kernel_entry = 0; 325 } 326 327 fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, 328 memmap[SPIKE_DRAM].size, 329 machine); 330 riscv_load_fdt(fdt_load_addr, machine->fdt); 331 332 /* load the reset vector */ 333 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, 334 memmap[SPIKE_MROM].base, 335 memmap[SPIKE_MROM].size, kernel_entry, 336 fdt_load_addr); 337 338 /* initialize HTIF using symbols found in load_kernel */ 339 htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base, 340 htif_custom_base); 341 } 342 343 static void spike_machine_instance_init(Object *obj) 344 { 345 } 346 347 static void spike_machine_class_init(ObjectClass *oc, void *data) 348 { 349 MachineClass *mc = MACHINE_CLASS(oc); 350 351 mc->desc = "RISC-V Spike board"; 352 mc->init = spike_board_init; 353 mc->max_cpus = SPIKE_CPUS_MAX; 354 mc->is_default = true; 355 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 356 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 357 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 358 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 359 mc->numa_mem_supported = true; 360 mc->default_ram_id = "riscv.spike.ram"; 361 } 362 363 static const TypeInfo spike_machine_typeinfo = { 364 .name = MACHINE_TYPE_NAME("spike"), 365 .parent = TYPE_MACHINE, 366 .class_init = spike_machine_class_init, 367 .instance_init = spike_machine_instance_init, 368 .instance_size = sizeof(SpikeState), 369 }; 370 371 static void spike_machine_init_register_types(void) 372 { 373 type_register_static(&spike_machine_typeinfo); 374 } 375 376 type_init(spike_machine_init_register_types) 377