1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/log.h" 28 #include "qemu/error-report.h" 29 #include "qapi/error.h" 30 #include "hw/hw.h" 31 #include "hw/boards.h" 32 #include "hw/loader.h" 33 #include "hw/sysbus.h" 34 #include "target/riscv/cpu.h" 35 #include "hw/riscv/riscv_htif.h" 36 #include "hw/riscv/riscv_hart.h" 37 #include "hw/riscv/sifive_clint.h" 38 #include "hw/riscv/spike.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "exec/address-spaces.h" 43 #include "elf.h" 44 45 static const struct MemmapEntry { 46 hwaddr base; 47 hwaddr size; 48 } spike_memmap[] = { 49 [SPIKE_MROM] = { 0x1000, 0x2000 }, 50 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 51 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 52 }; 53 54 static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) 55 { 56 int i; 57 for (i = 0; i < (len >> 2); i++) { 58 stl_phys(&address_space_memory, pa + (i << 2), rom[i]); 59 } 60 } 61 62 static uint64_t load_kernel(const char *kernel_filename) 63 { 64 uint64_t kernel_entry, kernel_high; 65 66 if (load_elf_ram_sym(kernel_filename, NULL, NULL, 67 &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, 68 NULL, true, htif_symbol_callback) < 0) { 69 error_report("qemu: could not load kernel '%s'", kernel_filename); 70 exit(1); 71 } 72 return kernel_entry; 73 } 74 75 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, 76 uint64_t mem_size, const char *cmdline) 77 { 78 void *fdt; 79 int cpu; 80 uint32_t *cells; 81 char *nodename; 82 83 fdt = s->fdt = create_device_tree(&s->fdt_size); 84 if (!fdt) { 85 error_report("create_device_tree() failed"); 86 exit(1); 87 } 88 89 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 90 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 91 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 92 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 93 94 qemu_fdt_add_subnode(fdt, "/htif"); 95 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 96 97 qemu_fdt_add_subnode(fdt, "/soc"); 98 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 99 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc"); 100 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 101 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 102 103 nodename = g_strdup_printf("/memory@%lx", 104 (long)memmap[SPIKE_DRAM].base); 105 qemu_fdt_add_subnode(fdt, nodename); 106 qemu_fdt_setprop_cells(fdt, nodename, "reg", 107 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base, 108 mem_size >> 32, mem_size); 109 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 110 g_free(nodename); 111 112 qemu_fdt_add_subnode(fdt, "/cpus"); 113 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 114 SIFIVE_CLINT_TIMEBASE_FREQ); 115 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 116 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 117 118 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 119 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 120 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 121 char *isa = riscv_isa_string(&s->soc.harts[cpu]); 122 qemu_fdt_add_subnode(fdt, nodename); 123 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 124 SPIKE_CLOCK_FREQ); 125 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 126 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 127 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 128 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 129 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 130 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 131 qemu_fdt_add_subnode(fdt, intc); 132 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); 133 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); 134 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 135 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 136 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 137 g_free(isa); 138 g_free(intc); 139 g_free(nodename); 140 } 141 142 cells = g_new0(uint32_t, s->soc.num_harts * 4); 143 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 144 nodename = 145 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 146 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 147 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 148 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 149 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 150 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 151 g_free(nodename); 152 } 153 nodename = g_strdup_printf("/soc/clint@%lx", 154 (long)memmap[SPIKE_CLINT].base); 155 qemu_fdt_add_subnode(fdt, nodename); 156 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 157 qemu_fdt_setprop_cells(fdt, nodename, "reg", 158 0x0, memmap[SPIKE_CLINT].base, 159 0x0, memmap[SPIKE_CLINT].size); 160 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 161 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 162 g_free(cells); 163 g_free(nodename); 164 165 qemu_fdt_add_subnode(fdt, "/chosen"); 166 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 167 } 168 169 static void spike_v1_10_0_board_init(MachineState *machine) 170 { 171 const struct MemmapEntry *memmap = spike_memmap; 172 173 SpikeState *s = g_new0(SpikeState, 1); 174 MemoryRegion *system_memory = get_system_memory(); 175 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 176 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 177 178 /* Initialize SOC */ 179 object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); 180 object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 181 &error_abort); 182 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type", 183 &error_abort); 184 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 185 &error_abort); 186 object_property_set_bool(OBJECT(&s->soc), true, "realized", 187 &error_abort); 188 189 /* register system main memory (actual RAM) */ 190 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 191 machine->ram_size, &error_fatal); 192 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 193 main_mem); 194 195 /* create device tree */ 196 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 197 198 /* boot rom */ 199 memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", 200 s->fdt_size + 0x2000, &error_fatal); 201 memory_region_add_subregion(system_memory, 0x0, boot_rom); 202 203 if (machine->kernel_filename) { 204 load_kernel(machine->kernel_filename); 205 } 206 207 /* reset vector */ 208 uint32_t reset_vec[8] = { 209 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 210 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 211 0xf1402573, /* csrr a0, mhartid */ 212 #if defined(TARGET_RISCV32) 213 0x0182a283, /* lw t0, 24(t0) */ 214 #elif defined(TARGET_RISCV64) 215 0x0182b283, /* ld t0, 24(t0) */ 216 #endif 217 0x00028067, /* jr t0 */ 218 0x00000000, 219 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ 220 0x00000000, 221 /* dtb: */ 222 }; 223 224 /* copy in the reset vector */ 225 copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec)); 226 227 /* copy in the device tree */ 228 qemu_fdt_dumpdtb(s->fdt, s->fdt_size); 229 cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), 230 s->fdt, s->fdt_size); 231 232 /* initialize HTIF using symbols found in load_kernel */ 233 htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); 234 235 /* Core Local Interruptor (timer and IPI) */ 236 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 237 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 238 } 239 240 static void spike_v1_09_1_board_init(MachineState *machine) 241 { 242 const struct MemmapEntry *memmap = spike_memmap; 243 244 SpikeState *s = g_new0(SpikeState, 1); 245 MemoryRegion *system_memory = get_system_memory(); 246 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 247 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 248 249 /* Initialize SOC */ 250 object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); 251 object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 252 &error_abort); 253 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type", 254 &error_abort); 255 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 256 &error_abort); 257 object_property_set_bool(OBJECT(&s->soc), true, "realized", 258 &error_abort); 259 260 /* register system main memory (actual RAM) */ 261 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 262 machine->ram_size, &error_fatal); 263 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 264 main_mem); 265 266 /* boot rom */ 267 memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", 268 0x40000, &error_fatal); 269 memory_region_add_subregion(system_memory, 0x0, boot_rom); 270 271 if (machine->kernel_filename) { 272 load_kernel(machine->kernel_filename); 273 } 274 275 /* reset vector */ 276 uint32_t reset_vec[8] = { 277 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */ 278 0x00028067, /* jump to DRAM_BASE */ 279 0x00000000, /* reserved */ 280 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */ 281 0, 0, 0, 0 /* trap vector */ 282 }; 283 284 /* part one of config string - before memory size specified */ 285 const char *config_string_tmpl = 286 "platform {\n" 287 " vendor ucb;\n" 288 " arch spike;\n" 289 "};\n" 290 "rtc {\n" 291 " addr 0x%" PRIx64 "x;\n" 292 "};\n" 293 "ram {\n" 294 " 0 {\n" 295 " addr 0x%" PRIx64 "x;\n" 296 " size 0x%" PRIx64 "x;\n" 297 " };\n" 298 "};\n" 299 "core {\n" 300 " 0" " {\n" 301 " " "0 {\n" 302 " isa %s;\n" 303 " timecmp 0x%" PRIx64 "x;\n" 304 " ipi 0x%" PRIx64 "x;\n" 305 " };\n" 306 " };\n" 307 "};\n"; 308 309 /* build config string with supplied memory size */ 310 char *isa = riscv_isa_string(&s->soc.harts[0]); 311 size_t config_string_size = strlen(config_string_tmpl) + 48; 312 char *config_string = malloc(config_string_size); 313 snprintf(config_string, config_string_size, config_string_tmpl, 314 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE, 315 (uint64_t)memmap[SPIKE_DRAM].base, 316 (uint64_t)ram_size, isa, 317 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE, 318 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE); 319 g_free(isa); 320 size_t config_string_len = strlen(config_string); 321 322 /* copy in the reset vector */ 323 copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec)); 324 325 /* copy in the config string */ 326 cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), 327 config_string, config_string_len); 328 329 /* initialize HTIF using symbols found in load_kernel */ 330 htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); 331 332 /* Core Local Interruptor (timer and IPI) */ 333 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 334 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 335 } 336 337 static void spike_v1_09_1_machine_init(MachineClass *mc) 338 { 339 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)"; 340 mc->init = spike_v1_09_1_board_init; 341 mc->max_cpus = 1; 342 } 343 344 static void spike_v1_10_0_machine_init(MachineClass *mc) 345 { 346 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)"; 347 mc->init = spike_v1_10_0_board_init; 348 mc->max_cpus = 1; 349 mc->is_default = 1; 350 } 351 352 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) 353 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) 354