1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/log.h" 28 #include "qemu/error-report.h" 29 #include "qapi/error.h" 30 #include "hw/hw.h" 31 #include "hw/boards.h" 32 #include "hw/loader.h" 33 #include "hw/sysbus.h" 34 #include "target/riscv/cpu.h" 35 #include "hw/riscv/riscv_htif.h" 36 #include "hw/riscv/riscv_hart.h" 37 #include "hw/riscv/sifive_clint.h" 38 #include "hw/riscv/spike.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/qtest.h" 43 #include "exec/address-spaces.h" 44 #include "elf.h" 45 46 #include <libfdt.h> 47 48 static const struct MemmapEntry { 49 hwaddr base; 50 hwaddr size; 51 } spike_memmap[] = { 52 [SPIKE_MROM] = { 0x1000, 0x11000 }, 53 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 54 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 55 }; 56 57 static target_ulong load_kernel(const char *kernel_filename) 58 { 59 uint64_t kernel_entry, kernel_high; 60 61 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 62 &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0, 63 NULL, true, htif_symbol_callback) < 0) { 64 error_report("could not load kernel '%s'", kernel_filename); 65 exit(1); 66 } 67 return kernel_entry; 68 } 69 70 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, 71 uint64_t mem_size, const char *cmdline) 72 { 73 void *fdt; 74 int cpu; 75 uint32_t *cells; 76 char *nodename; 77 78 fdt = s->fdt = create_device_tree(&s->fdt_size); 79 if (!fdt) { 80 error_report("create_device_tree() failed"); 81 exit(1); 82 } 83 84 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 85 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 86 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 87 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 88 89 qemu_fdt_add_subnode(fdt, "/htif"); 90 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 91 92 qemu_fdt_add_subnode(fdt, "/soc"); 93 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 94 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 95 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 96 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 97 98 nodename = g_strdup_printf("/memory@%lx", 99 (long)memmap[SPIKE_DRAM].base); 100 qemu_fdt_add_subnode(fdt, nodename); 101 qemu_fdt_setprop_cells(fdt, nodename, "reg", 102 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base, 103 mem_size >> 32, mem_size); 104 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 105 g_free(nodename); 106 107 qemu_fdt_add_subnode(fdt, "/cpus"); 108 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 109 SIFIVE_CLINT_TIMEBASE_FREQ); 110 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 111 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 112 113 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 114 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 115 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 116 char *isa = riscv_isa_string(&s->soc.harts[cpu]); 117 qemu_fdt_add_subnode(fdt, nodename); 118 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 119 SPIKE_CLOCK_FREQ); 120 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 121 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 122 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 123 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 124 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 125 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 126 qemu_fdt_add_subnode(fdt, intc); 127 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); 128 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); 129 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 130 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 131 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 132 g_free(isa); 133 g_free(intc); 134 g_free(nodename); 135 } 136 137 cells = g_new0(uint32_t, s->soc.num_harts * 4); 138 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 139 nodename = 140 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 141 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 142 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 143 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 144 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 145 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 146 g_free(nodename); 147 } 148 nodename = g_strdup_printf("/soc/clint@%lx", 149 (long)memmap[SPIKE_CLINT].base); 150 qemu_fdt_add_subnode(fdt, nodename); 151 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 152 qemu_fdt_setprop_cells(fdt, nodename, "reg", 153 0x0, memmap[SPIKE_CLINT].base, 154 0x0, memmap[SPIKE_CLINT].size); 155 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 156 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 157 g_free(cells); 158 g_free(nodename); 159 160 if (cmdline) { 161 qemu_fdt_add_subnode(fdt, "/chosen"); 162 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 163 } 164 } 165 166 static void spike_board_init(MachineState *machine) 167 { 168 const struct MemmapEntry *memmap = spike_memmap; 169 170 SpikeState *s = g_new0(SpikeState, 1); 171 MemoryRegion *system_memory = get_system_memory(); 172 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 173 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 174 int i; 175 176 /* Initialize SOC */ 177 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 178 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 179 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 180 &error_abort); 181 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 182 &error_abort); 183 object_property_set_bool(OBJECT(&s->soc), true, "realized", 184 &error_abort); 185 186 /* register system main memory (actual RAM) */ 187 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 188 machine->ram_size, &error_fatal); 189 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 190 main_mem); 191 192 /* create device tree */ 193 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 194 195 /* boot rom */ 196 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 197 memmap[SPIKE_MROM].size, &error_fatal); 198 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 199 mask_rom); 200 201 if (machine->kernel_filename) { 202 load_kernel(machine->kernel_filename); 203 } 204 205 /* reset vector */ 206 uint32_t reset_vec[8] = { 207 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 208 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 209 0xf1402573, /* csrr a0, mhartid */ 210 #if defined(TARGET_RISCV32) 211 0x0182a283, /* lw t0, 24(t0) */ 212 #elif defined(TARGET_RISCV64) 213 0x0182b283, /* ld t0, 24(t0) */ 214 #endif 215 0x00028067, /* jr t0 */ 216 0x00000000, 217 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ 218 0x00000000, 219 /* dtb: */ 220 }; 221 222 /* copy in the reset vector in little_endian byte order */ 223 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 224 reset_vec[i] = cpu_to_le32(reset_vec[i]); 225 } 226 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 227 memmap[SPIKE_MROM].base, &address_space_memory); 228 229 /* copy in the device tree */ 230 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 231 memmap[SPIKE_MROM].size - sizeof(reset_vec)) { 232 error_report("not enough space to store device-tree"); 233 exit(1); 234 } 235 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 236 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 237 memmap[SPIKE_MROM].base + sizeof(reset_vec), 238 &address_space_memory); 239 240 /* initialize HTIF using symbols found in load_kernel */ 241 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); 242 243 /* Core Local Interruptor (timer and IPI) */ 244 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 245 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 246 } 247 248 static void spike_v1_10_0_board_init(MachineState *machine) 249 { 250 const struct MemmapEntry *memmap = spike_memmap; 251 252 SpikeState *s = g_new0(SpikeState, 1); 253 MemoryRegion *system_memory = get_system_memory(); 254 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 255 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 256 int i; 257 258 if (!qtest_enabled()) { 259 info_report("The Spike v1.10.0 machine has been deprecated. " 260 "Please use the generic spike machine and specify the ISA " 261 "versions using -cpu."); 262 } 263 264 /* Initialize SOC */ 265 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 266 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 267 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type", 268 &error_abort); 269 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 270 &error_abort); 271 object_property_set_bool(OBJECT(&s->soc), true, "realized", 272 &error_abort); 273 274 /* register system main memory (actual RAM) */ 275 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 276 machine->ram_size, &error_fatal); 277 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 278 main_mem); 279 280 /* create device tree */ 281 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 282 283 /* boot rom */ 284 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 285 memmap[SPIKE_MROM].size, &error_fatal); 286 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 287 mask_rom); 288 289 if (machine->kernel_filename) { 290 load_kernel(machine->kernel_filename); 291 } 292 293 /* reset vector */ 294 uint32_t reset_vec[8] = { 295 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 296 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 297 0xf1402573, /* csrr a0, mhartid */ 298 #if defined(TARGET_RISCV32) 299 0x0182a283, /* lw t0, 24(t0) */ 300 #elif defined(TARGET_RISCV64) 301 0x0182b283, /* ld t0, 24(t0) */ 302 #endif 303 0x00028067, /* jr t0 */ 304 0x00000000, 305 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ 306 0x00000000, 307 /* dtb: */ 308 }; 309 310 /* copy in the reset vector in little_endian byte order */ 311 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 312 reset_vec[i] = cpu_to_le32(reset_vec[i]); 313 } 314 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 315 memmap[SPIKE_MROM].base, &address_space_memory); 316 317 /* copy in the device tree */ 318 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 319 memmap[SPIKE_MROM].size - sizeof(reset_vec)) { 320 error_report("not enough space to store device-tree"); 321 exit(1); 322 } 323 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 324 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 325 memmap[SPIKE_MROM].base + sizeof(reset_vec), 326 &address_space_memory); 327 328 /* initialize HTIF using symbols found in load_kernel */ 329 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); 330 331 /* Core Local Interruptor (timer and IPI) */ 332 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 333 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 334 } 335 336 static void spike_v1_09_1_board_init(MachineState *machine) 337 { 338 const struct MemmapEntry *memmap = spike_memmap; 339 340 SpikeState *s = g_new0(SpikeState, 1); 341 MemoryRegion *system_memory = get_system_memory(); 342 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 343 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 344 int i; 345 346 if (!qtest_enabled()) { 347 info_report("The Spike v1.09.1 machine has been deprecated. " 348 "Please use the generic spike machine and specify the ISA " 349 "versions using -cpu."); 350 } 351 352 /* Initialize SOC */ 353 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 354 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 355 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type", 356 &error_abort); 357 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 358 &error_abort); 359 object_property_set_bool(OBJECT(&s->soc), true, "realized", 360 &error_abort); 361 362 /* register system main memory (actual RAM) */ 363 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 364 machine->ram_size, &error_fatal); 365 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 366 main_mem); 367 368 /* boot rom */ 369 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 370 memmap[SPIKE_MROM].size, &error_fatal); 371 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 372 mask_rom); 373 374 if (machine->kernel_filename) { 375 load_kernel(machine->kernel_filename); 376 } 377 378 /* reset vector */ 379 uint32_t reset_vec[8] = { 380 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */ 381 0x00028067, /* jump to DRAM_BASE */ 382 0x00000000, /* reserved */ 383 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */ 384 0, 0, 0, 0 /* trap vector */ 385 }; 386 387 /* part one of config string - before memory size specified */ 388 const char *config_string_tmpl = 389 "platform {\n" 390 " vendor ucb;\n" 391 " arch spike;\n" 392 "};\n" 393 "rtc {\n" 394 " addr 0x%" PRIx64 "x;\n" 395 "};\n" 396 "ram {\n" 397 " 0 {\n" 398 " addr 0x%" PRIx64 "x;\n" 399 " size 0x%" PRIx64 "x;\n" 400 " };\n" 401 "};\n" 402 "core {\n" 403 " 0" " {\n" 404 " " "0 {\n" 405 " isa %s;\n" 406 " timecmp 0x%" PRIx64 "x;\n" 407 " ipi 0x%" PRIx64 "x;\n" 408 " };\n" 409 " };\n" 410 "};\n"; 411 412 /* build config string with supplied memory size */ 413 char *isa = riscv_isa_string(&s->soc.harts[0]); 414 char *config_string = g_strdup_printf(config_string_tmpl, 415 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE, 416 (uint64_t)memmap[SPIKE_DRAM].base, 417 (uint64_t)ram_size, isa, 418 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE, 419 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE); 420 g_free(isa); 421 size_t config_string_len = strlen(config_string); 422 423 /* copy in the reset vector in little_endian byte order */ 424 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 425 reset_vec[i] = cpu_to_le32(reset_vec[i]); 426 } 427 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 428 memmap[SPIKE_MROM].base, &address_space_memory); 429 430 /* copy in the config string */ 431 rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len, 432 memmap[SPIKE_MROM].base + sizeof(reset_vec), 433 &address_space_memory); 434 435 /* initialize HTIF using symbols found in load_kernel */ 436 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); 437 438 /* Core Local Interruptor (timer and IPI) */ 439 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 440 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 441 442 g_free(config_string); 443 } 444 445 static void spike_v1_09_1_machine_init(MachineClass *mc) 446 { 447 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)"; 448 mc->init = spike_v1_09_1_board_init; 449 mc->max_cpus = 1; 450 } 451 452 static void spike_v1_10_0_machine_init(MachineClass *mc) 453 { 454 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)"; 455 mc->init = spike_v1_10_0_board_init; 456 mc->max_cpus = 1; 457 } 458 459 static void spike_machine_init(MachineClass *mc) 460 { 461 mc->desc = "RISC-V Spike Board"; 462 mc->init = spike_board_init; 463 mc->max_cpus = 1; 464 mc->is_default = 1; 465 mc->default_cpu_type = SPIKE_V1_10_0_CPU; 466 } 467 468 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) 469 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) 470 DEFINE_MACHINE("spike", spike_machine_init) 471