1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 8) SPI0 connected to an SPI flash 19 * 9) SPI2 connected to an SD card 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qapi/error.h" 40 #include "qapi/visitor.h" 41 #include "hw/boards.h" 42 #include "hw/irq.h" 43 #include "hw/loader.h" 44 #include "hw/sysbus.h" 45 #include "hw/char/serial.h" 46 #include "hw/cpu/cluster.h" 47 #include "hw/misc/unimp.h" 48 #include "hw/ssi/ssi.h" 49 #include "target/riscv/cpu.h" 50 #include "hw/riscv/riscv_hart.h" 51 #include "hw/riscv/sifive_u.h" 52 #include "hw/riscv/boot.h" 53 #include "hw/char/sifive_uart.h" 54 #include "hw/intc/sifive_clint.h" 55 #include "hw/intc/sifive_plic.h" 56 #include "chardev/char.h" 57 #include "net/eth.h" 58 #include "sysemu/arch_init.h" 59 #include "sysemu/device_tree.h" 60 #include "sysemu/runstate.h" 61 #include "sysemu/sysemu.h" 62 63 #include <libfdt.h> 64 65 static const MemMapEntry sifive_u_memmap[] = { 66 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 67 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 68 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 69 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 70 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 71 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 72 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 73 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 74 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 75 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 76 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, 77 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, 78 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 79 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 80 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 81 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 82 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 83 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 84 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 85 }; 86 87 #define OTP_SERIAL 1 88 #define GEM_REVISION 0x10070109 89 90 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, 91 uint64_t mem_size, const char *cmdline, bool is_32_bit) 92 { 93 MachineState *ms = MACHINE(qdev_get_machine()); 94 void *fdt; 95 int cpu; 96 uint32_t *cells; 97 char *nodename; 98 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 99 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 100 static const char * const ethclk_names[2] = { "pclk", "hclk" }; 101 static const char * const clint_compat[2] = { 102 "sifive,clint0", "riscv,clint0" 103 }; 104 static const char * const plic_compat[2] = { 105 "sifive,plic-1.0.0", "riscv,plic0" 106 }; 107 108 if (ms->dtb) { 109 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); 110 if (!fdt) { 111 error_report("load_device_tree() failed"); 112 exit(1); 113 } 114 goto update_bootargs; 115 } else { 116 fdt = s->fdt = create_device_tree(&s->fdt_size); 117 if (!fdt) { 118 error_report("create_device_tree() failed"); 119 exit(1); 120 } 121 } 122 123 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 124 qemu_fdt_setprop_string(fdt, "/", "compatible", 125 "sifive,hifive-unleashed-a00"); 126 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 127 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 128 129 qemu_fdt_add_subnode(fdt, "/soc"); 130 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 131 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 132 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 133 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 134 135 hfclk_phandle = phandle++; 136 nodename = g_strdup_printf("/hfclk"); 137 qemu_fdt_add_subnode(fdt, nodename); 138 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 139 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 140 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 141 SIFIVE_U_HFCLK_FREQ); 142 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 143 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 144 g_free(nodename); 145 146 rtcclk_phandle = phandle++; 147 nodename = g_strdup_printf("/rtcclk"); 148 qemu_fdt_add_subnode(fdt, nodename); 149 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 150 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 151 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 152 SIFIVE_U_RTCCLK_FREQ); 153 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 154 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 155 g_free(nodename); 156 157 nodename = g_strdup_printf("/memory@%lx", 158 (long)memmap[SIFIVE_U_DEV_DRAM].base); 159 qemu_fdt_add_subnode(fdt, nodename); 160 qemu_fdt_setprop_cells(fdt, nodename, "reg", 161 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 162 mem_size >> 32, mem_size); 163 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 164 g_free(nodename); 165 166 qemu_fdt_add_subnode(fdt, "/cpus"); 167 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 168 SIFIVE_CLINT_TIMEBASE_FREQ); 169 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 170 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 171 172 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 173 int cpu_phandle = phandle++; 174 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 175 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 176 char *isa; 177 qemu_fdt_add_subnode(fdt, nodename); 178 /* cpu 0 is the management hart that does not have mmu */ 179 if (cpu != 0) { 180 if (is_32_bit) { 181 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 182 } else { 183 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 184 } 185 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 186 } else { 187 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 188 } 189 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 190 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 191 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 192 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 193 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 194 qemu_fdt_add_subnode(fdt, intc); 195 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 196 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 197 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 198 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 199 g_free(isa); 200 g_free(intc); 201 g_free(nodename); 202 } 203 204 cells = g_new0(uint32_t, ms->smp.cpus * 4); 205 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 206 nodename = 207 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 208 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 209 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 210 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 211 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 212 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 213 g_free(nodename); 214 } 215 nodename = g_strdup_printf("/soc/clint@%lx", 216 (long)memmap[SIFIVE_U_DEV_CLINT].base); 217 qemu_fdt_add_subnode(fdt, nodename); 218 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 219 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 220 qemu_fdt_setprop_cells(fdt, nodename, "reg", 221 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 222 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 223 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 224 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 225 g_free(cells); 226 g_free(nodename); 227 228 nodename = g_strdup_printf("/soc/otp@%lx", 229 (long)memmap[SIFIVE_U_DEV_OTP].base); 230 qemu_fdt_add_subnode(fdt, nodename); 231 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 232 qemu_fdt_setprop_cells(fdt, nodename, "reg", 233 0x0, memmap[SIFIVE_U_DEV_OTP].base, 234 0x0, memmap[SIFIVE_U_DEV_OTP].size); 235 qemu_fdt_setprop_string(fdt, nodename, "compatible", 236 "sifive,fu540-c000-otp"); 237 g_free(nodename); 238 239 prci_phandle = phandle++; 240 nodename = g_strdup_printf("/soc/clock-controller@%lx", 241 (long)memmap[SIFIVE_U_DEV_PRCI].base); 242 qemu_fdt_add_subnode(fdt, nodename); 243 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 244 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 245 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 246 hfclk_phandle, rtcclk_phandle); 247 qemu_fdt_setprop_cells(fdt, nodename, "reg", 248 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 249 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 250 qemu_fdt_setprop_string(fdt, nodename, "compatible", 251 "sifive,fu540-c000-prci"); 252 g_free(nodename); 253 254 plic_phandle = phandle++; 255 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 256 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 257 nodename = 258 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 259 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 260 /* cpu 0 is the management hart that does not have S-mode */ 261 if (cpu == 0) { 262 cells[0] = cpu_to_be32(intc_phandle); 263 cells[1] = cpu_to_be32(IRQ_M_EXT); 264 } else { 265 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 266 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 267 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 268 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 269 } 270 g_free(nodename); 271 } 272 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 273 (long)memmap[SIFIVE_U_DEV_PLIC].base); 274 qemu_fdt_add_subnode(fdt, nodename); 275 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 276 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 277 (char **)&plic_compat, ARRAY_SIZE(plic_compat)); 278 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 279 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 280 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 281 qemu_fdt_setprop_cells(fdt, nodename, "reg", 282 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 283 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 284 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 285 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 286 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 287 g_free(cells); 288 g_free(nodename); 289 290 gpio_phandle = phandle++; 291 nodename = g_strdup_printf("/soc/gpio@%lx", 292 (long)memmap[SIFIVE_U_DEV_GPIO].base); 293 qemu_fdt_add_subnode(fdt, nodename); 294 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 295 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 296 prci_phandle, PRCI_CLK_TLCLK); 297 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 298 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 299 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 300 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 301 qemu_fdt_setprop_cells(fdt, nodename, "reg", 302 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 303 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 304 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 305 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 306 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 307 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 308 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 309 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 310 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 311 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 312 g_free(nodename); 313 314 nodename = g_strdup_printf("/gpio-restart"); 315 qemu_fdt_add_subnode(fdt, nodename); 316 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 317 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 318 g_free(nodename); 319 320 nodename = g_strdup_printf("/soc/dma@%lx", 321 (long)memmap[SIFIVE_U_DEV_PDMA].base); 322 qemu_fdt_add_subnode(fdt, nodename); 323 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 324 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 325 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 326 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 327 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 328 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 329 qemu_fdt_setprop_cells(fdt, nodename, "reg", 330 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 331 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 332 qemu_fdt_setprop_string(fdt, nodename, "compatible", 333 "sifive,fu540-c000-pdma"); 334 g_free(nodename); 335 336 nodename = g_strdup_printf("/soc/cache-controller@%lx", 337 (long)memmap[SIFIVE_U_DEV_L2CC].base); 338 qemu_fdt_add_subnode(fdt, nodename); 339 qemu_fdt_setprop_cells(fdt, nodename, "reg", 340 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 341 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 342 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 343 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 344 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 345 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 346 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 347 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 348 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 349 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 350 qemu_fdt_setprop_string(fdt, nodename, "compatible", 351 "sifive,fu540-c000-ccache"); 352 g_free(nodename); 353 354 nodename = g_strdup_printf("/soc/spi@%lx", 355 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 356 qemu_fdt_add_subnode(fdt, nodename); 357 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 358 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 359 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 360 prci_phandle, PRCI_CLK_TLCLK); 361 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); 362 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 363 qemu_fdt_setprop_cells(fdt, nodename, "reg", 364 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, 365 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); 366 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 367 g_free(nodename); 368 369 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", 370 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 371 qemu_fdt_add_subnode(fdt, nodename); 372 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); 373 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); 374 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); 375 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 376 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); 377 g_free(nodename); 378 379 nodename = g_strdup_printf("/soc/spi@%lx", 380 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 381 qemu_fdt_add_subnode(fdt, nodename); 382 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 383 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 384 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 385 prci_phandle, PRCI_CLK_TLCLK); 386 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); 387 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 388 qemu_fdt_setprop_cells(fdt, nodename, "reg", 389 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, 390 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); 391 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 392 g_free(nodename); 393 394 nodename = g_strdup_printf("/soc/spi@%lx/flash@0", 395 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 396 qemu_fdt_add_subnode(fdt, nodename); 397 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); 398 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); 399 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); 400 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); 401 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 402 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); 403 g_free(nodename); 404 405 phy_phandle = phandle++; 406 nodename = g_strdup_printf("/soc/ethernet@%lx", 407 (long)memmap[SIFIVE_U_DEV_GEM].base); 408 qemu_fdt_add_subnode(fdt, nodename); 409 qemu_fdt_setprop_string(fdt, nodename, "compatible", 410 "sifive,fu540-c000-gem"); 411 qemu_fdt_setprop_cells(fdt, nodename, "reg", 412 0x0, memmap[SIFIVE_U_DEV_GEM].base, 413 0x0, memmap[SIFIVE_U_DEV_GEM].size, 414 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 415 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 416 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 417 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 418 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 419 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 420 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 421 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 422 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 423 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", 424 (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); 425 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 426 s->soc.gem.conf.macaddr.a, ETH_ALEN); 427 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 428 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 429 430 qemu_fdt_add_subnode(fdt, "/aliases"); 431 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 432 433 g_free(nodename); 434 435 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 436 (long)memmap[SIFIVE_U_DEV_GEM].base); 437 qemu_fdt_add_subnode(fdt, nodename); 438 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 439 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 440 g_free(nodename); 441 442 nodename = g_strdup_printf("/soc/serial@%lx", 443 (long)memmap[SIFIVE_U_DEV_UART1].base); 444 qemu_fdt_add_subnode(fdt, nodename); 445 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 446 qemu_fdt_setprop_cells(fdt, nodename, "reg", 447 0x0, memmap[SIFIVE_U_DEV_UART1].base, 448 0x0, memmap[SIFIVE_U_DEV_UART1].size); 449 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 450 prci_phandle, PRCI_CLK_TLCLK); 451 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 452 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); 453 454 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); 455 g_free(nodename); 456 457 nodename = g_strdup_printf("/soc/serial@%lx", 458 (long)memmap[SIFIVE_U_DEV_UART0].base); 459 qemu_fdt_add_subnode(fdt, nodename); 460 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 461 qemu_fdt_setprop_cells(fdt, nodename, "reg", 462 0x0, memmap[SIFIVE_U_DEV_UART0].base, 463 0x0, memmap[SIFIVE_U_DEV_UART0].size); 464 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 465 prci_phandle, PRCI_CLK_TLCLK); 466 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 467 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 468 469 qemu_fdt_add_subnode(fdt, "/chosen"); 470 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 471 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 472 473 g_free(nodename); 474 475 update_bootargs: 476 if (cmdline) { 477 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 478 } 479 } 480 481 static void sifive_u_machine_reset(void *opaque, int n, int level) 482 { 483 /* gpio pin active low triggers reset */ 484 if (!level) { 485 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 486 } 487 } 488 489 static void sifive_u_machine_init(MachineState *machine) 490 { 491 const MemMapEntry *memmap = sifive_u_memmap; 492 SiFiveUState *s = RISCV_U_MACHINE(machine); 493 MemoryRegion *system_memory = get_system_memory(); 494 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 495 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 496 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 497 target_ulong firmware_end_addr, kernel_start_addr; 498 uint32_t start_addr_hi32 = 0x00000000; 499 int i; 500 uint32_t fdt_load_addr; 501 uint64_t kernel_entry; 502 DriveInfo *dinfo; 503 DeviceState *flash_dev, *sd_dev; 504 qemu_irq flash_cs, sd_cs; 505 506 /* Initialize SoC */ 507 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 508 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 509 &error_abort); 510 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 511 &error_abort); 512 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 513 514 /* register RAM */ 515 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 516 machine->ram_size, &error_fatal); 517 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 518 main_mem); 519 520 /* register QSPI0 Flash */ 521 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 522 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 523 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 524 flash0); 525 526 /* register gpio-restart */ 527 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 528 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 529 530 /* create device tree */ 531 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 532 riscv_is_32bit(&s->soc.u_cpus)); 533 534 if (s->start_in_flash) { 535 /* 536 * If start_in_flash property is given, assign s->msel to a value 537 * that representing booting from QSPI0 memory-mapped flash. 538 * 539 * This also means that when both start_in_flash and msel properties 540 * are given, start_in_flash takes the precedence over msel. 541 * 542 * Note this is to keep backward compatibility not to break existing 543 * users that use start_in_flash property. 544 */ 545 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 546 } 547 548 switch (s->msel) { 549 case MSEL_MEMMAP_QSPI0_FLASH: 550 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 551 break; 552 case MSEL_L2LIM_QSPI0_FLASH: 553 case MSEL_L2LIM_QSPI2_SD: 554 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 555 break; 556 default: 557 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 558 break; 559 } 560 561 if (riscv_is_32bit(&s->soc.u_cpus)) { 562 firmware_end_addr = riscv_find_and_load_firmware(machine, 563 RISCV32_BIOS_BIN, start_addr, NULL); 564 } else { 565 firmware_end_addr = riscv_find_and_load_firmware(machine, 566 RISCV64_BIOS_BIN, start_addr, NULL); 567 } 568 569 if (machine->kernel_filename) { 570 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 571 firmware_end_addr); 572 573 kernel_entry = riscv_load_kernel(machine->kernel_filename, 574 kernel_start_addr, NULL); 575 576 if (machine->initrd_filename) { 577 hwaddr start; 578 hwaddr end = riscv_load_initrd(machine->initrd_filename, 579 machine->ram_size, kernel_entry, 580 &start); 581 qemu_fdt_setprop_cell(s->fdt, "/chosen", 582 "linux,initrd-start", start); 583 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 584 end); 585 } 586 } else { 587 /* 588 * If dynamic firmware is used, it doesn't know where is the next mode 589 * if kernel argument is not set. 590 */ 591 kernel_entry = 0; 592 } 593 594 /* Compute the fdt load address in dram */ 595 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, 596 machine->ram_size, s->fdt); 597 if (!riscv_is_32bit(&s->soc.u_cpus)) { 598 start_addr_hi32 = (uint64_t)start_addr >> 32; 599 } 600 601 /* reset vector */ 602 uint32_t reset_vec[11] = { 603 s->msel, /* MSEL pin state */ 604 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 605 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 606 0xf1402573, /* csrr a0, mhartid */ 607 0, 608 0, 609 0x00028067, /* jr t0 */ 610 start_addr, /* start: .dword */ 611 start_addr_hi32, 612 fdt_load_addr, /* fdt_laddr: .dword */ 613 0x00000000, 614 /* fw_dyn: */ 615 }; 616 if (riscv_is_32bit(&s->soc.u_cpus)) { 617 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ 618 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ 619 } else { 620 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ 621 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ 622 } 623 624 625 /* copy in the reset vector in little_endian byte order */ 626 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 627 reset_vec[i] = cpu_to_le32(reset_vec[i]); 628 } 629 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 630 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 631 632 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, 633 memmap[SIFIVE_U_DEV_MROM].size, 634 sizeof(reset_vec), kernel_entry); 635 636 /* Connect an SPI flash to SPI0 */ 637 flash_dev = qdev_new("is25wp256"); 638 dinfo = drive_get_next(IF_MTD); 639 if (dinfo) { 640 qdev_prop_set_drive_err(flash_dev, "drive", 641 blk_by_legacy_dinfo(dinfo), 642 &error_fatal); 643 } 644 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); 645 646 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 647 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); 648 649 /* Connect an SD card to SPI2 */ 650 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); 651 652 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); 653 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); 654 } 655 656 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 657 { 658 SiFiveUState *s = RISCV_U_MACHINE(obj); 659 660 return s->start_in_flash; 661 } 662 663 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 664 { 665 SiFiveUState *s = RISCV_U_MACHINE(obj); 666 667 s->start_in_flash = value; 668 } 669 670 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 671 const char *name, void *opaque, 672 Error **errp) 673 { 674 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 675 } 676 677 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 678 const char *name, void *opaque, 679 Error **errp) 680 { 681 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 682 } 683 684 static void sifive_u_machine_instance_init(Object *obj) 685 { 686 SiFiveUState *s = RISCV_U_MACHINE(obj); 687 688 s->start_in_flash = false; 689 s->msel = 0; 690 object_property_add(obj, "msel", "uint32", 691 sifive_u_machine_get_uint32_prop, 692 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 693 object_property_set_description(obj, "msel", 694 "Mode Select (MSEL[3:0]) pin state"); 695 696 s->serial = OTP_SERIAL; 697 object_property_add(obj, "serial", "uint32", 698 sifive_u_machine_get_uint32_prop, 699 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 700 object_property_set_description(obj, "serial", "Board serial number"); 701 } 702 703 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 704 { 705 MachineClass *mc = MACHINE_CLASS(oc); 706 707 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 708 mc->init = sifive_u_machine_init; 709 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 710 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 711 mc->default_cpu_type = SIFIVE_U_CPU; 712 mc->default_cpus = mc->min_cpus; 713 714 object_class_property_add_bool(oc, "start-in-flash", 715 sifive_u_machine_get_start_in_flash, 716 sifive_u_machine_set_start_in_flash); 717 object_class_property_set_description(oc, "start-in-flash", 718 "Set on to tell QEMU's ROM to jump to " 719 "flash. Otherwise QEMU will jump to DRAM " 720 "or L2LIM depending on the msel value"); 721 } 722 723 static const TypeInfo sifive_u_machine_typeinfo = { 724 .name = MACHINE_TYPE_NAME("sifive_u"), 725 .parent = TYPE_MACHINE, 726 .class_init = sifive_u_machine_class_init, 727 .instance_init = sifive_u_machine_instance_init, 728 .instance_size = sizeof(SiFiveUState), 729 }; 730 731 static void sifive_u_machine_init_register_types(void) 732 { 733 type_register_static(&sifive_u_machine_typeinfo); 734 } 735 736 type_init(sifive_u_machine_init_register_types) 737 738 static void sifive_u_soc_instance_init(Object *obj) 739 { 740 SiFiveUSoCState *s = RISCV_U_SOC(obj); 741 742 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 743 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 744 745 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 746 TYPE_RISCV_HART_ARRAY); 747 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 748 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 749 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 750 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 751 752 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 753 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 754 755 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 756 TYPE_RISCV_HART_ARRAY); 757 758 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 759 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 760 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 761 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 762 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 763 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); 764 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); 765 } 766 767 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 768 { 769 MachineState *ms = MACHINE(qdev_get_machine()); 770 SiFiveUSoCState *s = RISCV_U_SOC(dev); 771 const MemMapEntry *memmap = sifive_u_memmap; 772 MemoryRegion *system_memory = get_system_memory(); 773 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 774 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 775 char *plic_hart_config; 776 size_t plic_hart_config_len; 777 int i; 778 NICInfo *nd = &nd_table[0]; 779 780 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 781 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 782 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 783 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 784 785 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 786 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 787 /* 788 * The cluster must be realized after the RISC-V hart array container, 789 * as the container's CPU object is only created on realize, and the 790 * CPU must exist and have been parented into the cluster before the 791 * cluster is realized. 792 */ 793 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 794 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 795 796 /* boot rom */ 797 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 798 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 799 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 800 mask_rom); 801 802 /* 803 * Add L2-LIM at reset size. 804 * This should be reduced in size as the L2 Cache Controller WayEnable 805 * register is incremented. Unfortunately I don't see a nice (or any) way 806 * to handle reducing or blocking out the L2 LIM while still allowing it 807 * be re returned to all enabled after a reset. For the time being, just 808 * leave it enabled all the time. This won't break anything, but will be 809 * too generous to misbehaving guests. 810 */ 811 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 812 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 813 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 814 l2lim_mem); 815 816 /* create PLIC hart topology configuration string */ 817 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 818 ms->smp.cpus; 819 plic_hart_config = g_malloc0(plic_hart_config_len); 820 for (i = 0; i < ms->smp.cpus; i++) { 821 if (i != 0) { 822 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 823 plic_hart_config_len); 824 } else { 825 strncat(plic_hart_config, "M", plic_hart_config_len); 826 } 827 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 828 } 829 830 /* MMIO */ 831 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 832 plic_hart_config, 0, 833 SIFIVE_U_PLIC_NUM_SOURCES, 834 SIFIVE_U_PLIC_NUM_PRIORITIES, 835 SIFIVE_U_PLIC_PRIORITY_BASE, 836 SIFIVE_U_PLIC_PENDING_BASE, 837 SIFIVE_U_PLIC_ENABLE_BASE, 838 SIFIVE_U_PLIC_ENABLE_STRIDE, 839 SIFIVE_U_PLIC_CONTEXT_BASE, 840 SIFIVE_U_PLIC_CONTEXT_STRIDE, 841 memmap[SIFIVE_U_DEV_PLIC].size); 842 g_free(plic_hart_config); 843 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 844 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 845 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 846 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 847 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, 848 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, 849 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 850 SIFIVE_CLINT_TIMEBASE_FREQ, false); 851 852 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 853 return; 854 } 855 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 856 857 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 858 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 859 return; 860 } 861 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 862 863 /* Pass all GPIOs to the SOC layer so they are available to the board */ 864 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 865 866 /* Connect GPIO interrupts to the PLIC */ 867 for (i = 0; i < 16; i++) { 868 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 869 qdev_get_gpio_in(DEVICE(s->plic), 870 SIFIVE_U_GPIO_IRQ0 + i)); 871 } 872 873 /* PDMA */ 874 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 875 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 876 877 /* Connect PDMA interrupts to the PLIC */ 878 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 879 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 880 qdev_get_gpio_in(DEVICE(s->plic), 881 SIFIVE_U_PDMA_IRQ0 + i)); 882 } 883 884 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 885 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 886 return; 887 } 888 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 889 890 /* FIXME use qdev NIC properties instead of nd_table[] */ 891 if (nd->used) { 892 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 893 qdev_set_nic_properties(DEVICE(&s->gem), nd); 894 } 895 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 896 &error_abort); 897 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 898 return; 899 } 900 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 901 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 902 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 903 904 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 905 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 906 907 create_unimplemented_device("riscv.sifive.u.dmc", 908 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 909 910 create_unimplemented_device("riscv.sifive.u.l2cc", 911 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 912 913 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); 914 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, 915 memmap[SIFIVE_U_DEV_QSPI0].base); 916 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, 917 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); 918 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); 919 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, 920 memmap[SIFIVE_U_DEV_QSPI2].base); 921 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, 922 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); 923 } 924 925 static Property sifive_u_soc_props[] = { 926 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 927 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 928 DEFINE_PROP_END_OF_LIST() 929 }; 930 931 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 932 { 933 DeviceClass *dc = DEVICE_CLASS(oc); 934 935 device_class_set_props(dc, sifive_u_soc_props); 936 dc->realize = sifive_u_soc_realize; 937 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 938 dc->user_creatable = false; 939 } 940 941 static const TypeInfo sifive_u_soc_type_info = { 942 .name = TYPE_RISCV_U_SOC, 943 .parent = TYPE_DEVICE, 944 .instance_size = sizeof(SiFiveUSoCState), 945 .instance_init = sifive_u_soc_instance_init, 946 .class_init = sifive_u_soc_class_init, 947 }; 948 949 static void sifive_u_soc_register_types(void) 950 { 951 type_register_static(&sifive_u_soc_type_info); 952 } 953 954 type_init(sifive_u_soc_register_types) 955