1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 8) SPI0 connected to an SPI flash 19 * 9) SPI2 connected to an SD card 20 * 10) PWM0 and PWM1 21 * 22 * This board currently generates devicetree dynamically that indicates at least 23 * two harts and up to five harts. 24 * 25 * This program is free software; you can redistribute it and/or modify it 26 * under the terms and conditions of the GNU General Public License, 27 * version 2 or later, as published by the Free Software Foundation. 28 * 29 * This program is distributed in the hope it will be useful, but WITHOUT 30 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 31 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 32 * more details. 33 * 34 * You should have received a copy of the GNU General Public License along with 35 * this program. If not, see <http://www.gnu.org/licenses/>. 36 */ 37 38 #include "qemu/osdep.h" 39 #include "qemu/error-report.h" 40 #include "qapi/error.h" 41 #include "qapi/visitor.h" 42 #include "hw/boards.h" 43 #include "hw/irq.h" 44 #include "hw/loader.h" 45 #include "hw/sysbus.h" 46 #include "hw/char/serial.h" 47 #include "hw/cpu/cluster.h" 48 #include "hw/misc/unimp.h" 49 #include "hw/sd/sd.h" 50 #include "hw/ssi/ssi.h" 51 #include "target/riscv/cpu.h" 52 #include "hw/riscv/riscv_hart.h" 53 #include "hw/riscv/sifive_u.h" 54 #include "hw/riscv/boot.h" 55 #include "hw/char/sifive_uart.h" 56 #include "hw/intc/riscv_aclint.h" 57 #include "hw/intc/sifive_plic.h" 58 #include "chardev/char.h" 59 #include "net/eth.h" 60 #include "sysemu/device_tree.h" 61 #include "sysemu/runstate.h" 62 #include "sysemu/sysemu.h" 63 64 #include <libfdt.h> 65 66 /* CLINT timebase frequency */ 67 #define CLINT_TIMEBASE_FREQ 1000000 68 69 static const MemMapEntry sifive_u_memmap[] = { 70 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 71 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 72 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 73 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 74 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 75 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 76 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 77 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 78 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 79 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 80 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 }, 81 [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 }, 82 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, 83 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, 84 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 85 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 86 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 87 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 88 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 89 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 90 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 91 }; 92 93 #define OTP_SERIAL 1 94 #define GEM_REVISION 0x10070109 95 96 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, 97 bool is_32_bit) 98 { 99 MachineState *ms = MACHINE(s); 100 uint64_t mem_size = ms->ram_size; 101 void *fdt; 102 int cpu, fdt_size; 103 uint32_t *cells; 104 char *nodename; 105 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 106 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 107 static const char * const ethclk_names[2] = { "pclk", "hclk" }; 108 static const char * const clint_compat[2] = { 109 "sifive,clint0", "riscv,clint0" 110 }; 111 static const char * const plic_compat[2] = { 112 "sifive,plic-1.0.0", "riscv,plic0" 113 }; 114 115 if (ms->dtb) { 116 fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size); 117 if (!fdt) { 118 error_report("load_device_tree() failed"); 119 exit(1); 120 } 121 } else { 122 fdt = ms->fdt = create_device_tree(&fdt_size); 123 if (!fdt) { 124 error_report("create_device_tree() failed"); 125 exit(1); 126 } 127 } 128 129 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 130 qemu_fdt_setprop_string(fdt, "/", "compatible", 131 "sifive,hifive-unleashed-a00"); 132 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 133 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 134 135 qemu_fdt_add_subnode(fdt, "/soc"); 136 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 137 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 138 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 139 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 140 141 hfclk_phandle = phandle++; 142 nodename = g_strdup_printf("/hfclk"); 143 qemu_fdt_add_subnode(fdt, nodename); 144 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 145 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 146 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 147 SIFIVE_U_HFCLK_FREQ); 148 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 149 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 150 g_free(nodename); 151 152 rtcclk_phandle = phandle++; 153 nodename = g_strdup_printf("/rtcclk"); 154 qemu_fdt_add_subnode(fdt, nodename); 155 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 156 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 157 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 158 SIFIVE_U_RTCCLK_FREQ); 159 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 160 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 161 g_free(nodename); 162 163 nodename = g_strdup_printf("/memory@%lx", 164 (long)memmap[SIFIVE_U_DEV_DRAM].base); 165 qemu_fdt_add_subnode(fdt, nodename); 166 qemu_fdt_setprop_cells(fdt, nodename, "reg", 167 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 168 mem_size >> 32, mem_size); 169 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 170 g_free(nodename); 171 172 qemu_fdt_add_subnode(fdt, "/cpus"); 173 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 174 CLINT_TIMEBASE_FREQ); 175 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 176 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 177 178 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 179 int cpu_phandle = phandle++; 180 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 181 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 182 char *isa; 183 qemu_fdt_add_subnode(fdt, nodename); 184 /* cpu 0 is the management hart that does not have mmu */ 185 if (cpu != 0) { 186 if (is_32_bit) { 187 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 188 } else { 189 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 190 } 191 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 192 } else { 193 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 194 } 195 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 196 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 197 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 198 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 199 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 200 qemu_fdt_add_subnode(fdt, intc); 201 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 202 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 203 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 204 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 205 g_free(isa); 206 g_free(intc); 207 g_free(nodename); 208 } 209 210 cells = g_new0(uint32_t, ms->smp.cpus * 4); 211 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 212 nodename = 213 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 214 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 215 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 216 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 217 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 218 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 219 g_free(nodename); 220 } 221 nodename = g_strdup_printf("/soc/clint@%lx", 222 (long)memmap[SIFIVE_U_DEV_CLINT].base); 223 qemu_fdt_add_subnode(fdt, nodename); 224 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 225 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 226 qemu_fdt_setprop_cells(fdt, nodename, "reg", 227 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 228 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 229 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 230 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 231 g_free(cells); 232 g_free(nodename); 233 234 nodename = g_strdup_printf("/soc/otp@%lx", 235 (long)memmap[SIFIVE_U_DEV_OTP].base); 236 qemu_fdt_add_subnode(fdt, nodename); 237 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 238 qemu_fdt_setprop_cells(fdt, nodename, "reg", 239 0x0, memmap[SIFIVE_U_DEV_OTP].base, 240 0x0, memmap[SIFIVE_U_DEV_OTP].size); 241 qemu_fdt_setprop_string(fdt, nodename, "compatible", 242 "sifive,fu540-c000-otp"); 243 g_free(nodename); 244 245 prci_phandle = phandle++; 246 nodename = g_strdup_printf("/soc/clock-controller@%lx", 247 (long)memmap[SIFIVE_U_DEV_PRCI].base); 248 qemu_fdt_add_subnode(fdt, nodename); 249 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 250 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 251 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 252 hfclk_phandle, rtcclk_phandle); 253 qemu_fdt_setprop_cells(fdt, nodename, "reg", 254 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 255 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 256 qemu_fdt_setprop_string(fdt, nodename, "compatible", 257 "sifive,fu540-c000-prci"); 258 g_free(nodename); 259 260 plic_phandle = phandle++; 261 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 262 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 263 nodename = 264 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 265 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 266 /* cpu 0 is the management hart that does not have S-mode */ 267 if (cpu == 0) { 268 cells[0] = cpu_to_be32(intc_phandle); 269 cells[1] = cpu_to_be32(IRQ_M_EXT); 270 } else { 271 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 272 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 273 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 274 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 275 } 276 g_free(nodename); 277 } 278 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 279 (long)memmap[SIFIVE_U_DEV_PLIC].base); 280 qemu_fdt_add_subnode(fdt, nodename); 281 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 282 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 283 (char **)&plic_compat, ARRAY_SIZE(plic_compat)); 284 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 285 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 286 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 287 qemu_fdt_setprop_cells(fdt, nodename, "reg", 288 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 289 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 290 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 291 SIFIVE_U_PLIC_NUM_SOURCES - 1); 292 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 293 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 294 g_free(cells); 295 g_free(nodename); 296 297 gpio_phandle = phandle++; 298 nodename = g_strdup_printf("/soc/gpio@%lx", 299 (long)memmap[SIFIVE_U_DEV_GPIO].base); 300 qemu_fdt_add_subnode(fdt, nodename); 301 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 302 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 303 prci_phandle, PRCI_CLK_TLCLK); 304 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 305 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 306 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 307 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 308 qemu_fdt_setprop_cells(fdt, nodename, "reg", 309 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 310 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 311 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 312 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 313 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 314 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 315 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 316 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 317 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 318 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 319 g_free(nodename); 320 321 nodename = g_strdup_printf("/gpio-restart"); 322 qemu_fdt_add_subnode(fdt, nodename); 323 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 324 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 325 g_free(nodename); 326 327 nodename = g_strdup_printf("/soc/dma@%lx", 328 (long)memmap[SIFIVE_U_DEV_PDMA].base); 329 qemu_fdt_add_subnode(fdt, nodename); 330 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 331 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 332 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 333 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 334 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 335 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 336 qemu_fdt_setprop_cells(fdt, nodename, "reg", 337 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 338 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 339 qemu_fdt_setprop_string(fdt, nodename, "compatible", 340 "sifive,fu540-c000-pdma"); 341 g_free(nodename); 342 343 nodename = g_strdup_printf("/soc/cache-controller@%lx", 344 (long)memmap[SIFIVE_U_DEV_L2CC].base); 345 qemu_fdt_add_subnode(fdt, nodename); 346 qemu_fdt_setprop_cells(fdt, nodename, "reg", 347 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 348 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 349 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 350 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 351 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 352 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 353 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 354 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 355 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 356 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 357 qemu_fdt_setprop_string(fdt, nodename, "compatible", 358 "sifive,fu540-c000-ccache"); 359 g_free(nodename); 360 361 nodename = g_strdup_printf("/soc/spi@%lx", 362 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 363 qemu_fdt_add_subnode(fdt, nodename); 364 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 365 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 366 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 367 prci_phandle, PRCI_CLK_TLCLK); 368 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); 369 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 370 qemu_fdt_setprop_cells(fdt, nodename, "reg", 371 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, 372 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); 373 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 374 g_free(nodename); 375 376 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", 377 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 378 qemu_fdt_add_subnode(fdt, nodename); 379 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); 380 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); 381 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); 382 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 383 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); 384 g_free(nodename); 385 386 nodename = g_strdup_printf("/soc/spi@%lx", 387 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 388 qemu_fdt_add_subnode(fdt, nodename); 389 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 390 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 391 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 392 prci_phandle, PRCI_CLK_TLCLK); 393 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); 394 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 395 qemu_fdt_setprop_cells(fdt, nodename, "reg", 396 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, 397 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); 398 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 399 g_free(nodename); 400 401 nodename = g_strdup_printf("/soc/spi@%lx/flash@0", 402 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 403 qemu_fdt_add_subnode(fdt, nodename); 404 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); 405 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); 406 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); 407 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); 408 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 409 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); 410 g_free(nodename); 411 412 phy_phandle = phandle++; 413 nodename = g_strdup_printf("/soc/ethernet@%lx", 414 (long)memmap[SIFIVE_U_DEV_GEM].base); 415 qemu_fdt_add_subnode(fdt, nodename); 416 qemu_fdt_setprop_string(fdt, nodename, "compatible", 417 "sifive,fu540-c000-gem"); 418 qemu_fdt_setprop_cells(fdt, nodename, "reg", 419 0x0, memmap[SIFIVE_U_DEV_GEM].base, 420 0x0, memmap[SIFIVE_U_DEV_GEM].size, 421 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 422 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 423 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 424 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 425 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 426 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 427 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 428 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 429 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 430 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", 431 (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); 432 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 433 s->soc.gem.conf.macaddr.a, ETH_ALEN); 434 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 435 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 436 437 qemu_fdt_add_subnode(fdt, "/aliases"); 438 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 439 440 g_free(nodename); 441 442 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 443 (long)memmap[SIFIVE_U_DEV_GEM].base); 444 qemu_fdt_add_subnode(fdt, nodename); 445 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 446 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 447 g_free(nodename); 448 449 nodename = g_strdup_printf("/soc/pwm@%lx", 450 (long)memmap[SIFIVE_U_DEV_PWM0].base); 451 qemu_fdt_add_subnode(fdt, nodename); 452 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); 453 qemu_fdt_setprop_cells(fdt, nodename, "reg", 454 0x0, memmap[SIFIVE_U_DEV_PWM0].base, 455 0x0, memmap[SIFIVE_U_DEV_PWM0].size); 456 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 457 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 458 SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, 459 SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3); 460 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 461 prci_phandle, PRCI_CLK_TLCLK); 462 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); 463 g_free(nodename); 464 465 nodename = g_strdup_printf("/soc/pwm@%lx", 466 (long)memmap[SIFIVE_U_DEV_PWM1].base); 467 qemu_fdt_add_subnode(fdt, nodename); 468 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); 469 qemu_fdt_setprop_cells(fdt, nodename, "reg", 470 0x0, memmap[SIFIVE_U_DEV_PWM1].base, 471 0x0, memmap[SIFIVE_U_DEV_PWM1].size); 472 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 473 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 474 SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1, 475 SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3); 476 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 477 prci_phandle, PRCI_CLK_TLCLK); 478 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); 479 g_free(nodename); 480 481 nodename = g_strdup_printf("/soc/serial@%lx", 482 (long)memmap[SIFIVE_U_DEV_UART1].base); 483 qemu_fdt_add_subnode(fdt, nodename); 484 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 485 qemu_fdt_setprop_cells(fdt, nodename, "reg", 486 0x0, memmap[SIFIVE_U_DEV_UART1].base, 487 0x0, memmap[SIFIVE_U_DEV_UART1].size); 488 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 489 prci_phandle, PRCI_CLK_TLCLK); 490 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 491 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); 492 493 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); 494 g_free(nodename); 495 496 nodename = g_strdup_printf("/soc/serial@%lx", 497 (long)memmap[SIFIVE_U_DEV_UART0].base); 498 qemu_fdt_add_subnode(fdt, nodename); 499 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 500 qemu_fdt_setprop_cells(fdt, nodename, "reg", 501 0x0, memmap[SIFIVE_U_DEV_UART0].base, 502 0x0, memmap[SIFIVE_U_DEV_UART0].size); 503 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 504 prci_phandle, PRCI_CLK_TLCLK); 505 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 506 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 507 508 qemu_fdt_add_subnode(fdt, "/chosen"); 509 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 510 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 511 512 g_free(nodename); 513 } 514 515 static void sifive_u_machine_reset(void *opaque, int n, int level) 516 { 517 /* gpio pin active low triggers reset */ 518 if (!level) { 519 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 520 } 521 } 522 523 static void sifive_u_machine_init(MachineState *machine) 524 { 525 const MemMapEntry *memmap = sifive_u_memmap; 526 SiFiveUState *s = RISCV_U_MACHINE(machine); 527 MemoryRegion *system_memory = get_system_memory(); 528 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 529 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 530 target_ulong firmware_end_addr, kernel_start_addr; 531 const char *firmware_name; 532 uint32_t start_addr_hi32 = 0x00000000; 533 int i; 534 uint32_t fdt_load_addr; 535 uint64_t kernel_entry; 536 DriveInfo *dinfo; 537 BlockBackend *blk; 538 DeviceState *flash_dev, *sd_dev, *card_dev; 539 qemu_irq flash_cs, sd_cs; 540 541 /* Initialize SoC */ 542 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 543 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 544 &error_abort); 545 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 546 &error_abort); 547 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 548 549 /* register RAM */ 550 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 551 machine->ram); 552 553 /* register QSPI0 Flash */ 554 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 555 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 556 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 557 flash0); 558 559 /* register gpio-restart */ 560 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 561 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 562 563 /* create device tree */ 564 create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); 565 566 if (s->start_in_flash) { 567 /* 568 * If start_in_flash property is given, assign s->msel to a value 569 * that representing booting from QSPI0 memory-mapped flash. 570 * 571 * This also means that when both start_in_flash and msel properties 572 * are given, start_in_flash takes the precedence over msel. 573 * 574 * Note this is to keep backward compatibility not to break existing 575 * users that use start_in_flash property. 576 */ 577 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 578 } 579 580 switch (s->msel) { 581 case MSEL_MEMMAP_QSPI0_FLASH: 582 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 583 break; 584 case MSEL_L2LIM_QSPI0_FLASH: 585 case MSEL_L2LIM_QSPI2_SD: 586 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 587 break; 588 default: 589 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 590 break; 591 } 592 593 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); 594 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 595 start_addr, NULL); 596 597 if (machine->kernel_filename) { 598 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 599 firmware_end_addr); 600 601 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, 602 kernel_start_addr, true, NULL); 603 } else { 604 /* 605 * If dynamic firmware is used, it doesn't know where is the next mode 606 * if kernel argument is not set. 607 */ 608 kernel_entry = 0; 609 } 610 611 fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, 612 memmap[SIFIVE_U_DEV_DRAM].size, 613 machine); 614 riscv_load_fdt(fdt_load_addr, machine->fdt); 615 616 if (!riscv_is_32bit(&s->soc.u_cpus)) { 617 start_addr_hi32 = (uint64_t)start_addr >> 32; 618 } 619 620 /* reset vector */ 621 uint32_t reset_vec[12] = { 622 s->msel, /* MSEL pin state */ 623 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 624 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ 625 0xf1402573, /* csrr a0, mhartid */ 626 0, 627 0, 628 0x00028067, /* jr t0 */ 629 start_addr, /* start: .dword */ 630 start_addr_hi32, 631 fdt_load_addr, /* fdt_laddr: .dword */ 632 0x00000000, 633 0x00000000, 634 /* fw_dyn: */ 635 }; 636 if (riscv_is_32bit(&s->soc.u_cpus)) { 637 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ 638 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ 639 } else { 640 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ 641 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ 642 } 643 644 645 /* copy in the reset vector in little_endian byte order */ 646 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 647 reset_vec[i] = cpu_to_le32(reset_vec[i]); 648 } 649 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 650 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 651 652 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, 653 memmap[SIFIVE_U_DEV_MROM].size, 654 sizeof(reset_vec), kernel_entry); 655 656 /* Connect an SPI flash to SPI0 */ 657 flash_dev = qdev_new("is25wp256"); 658 dinfo = drive_get(IF_MTD, 0, 0); 659 if (dinfo) { 660 qdev_prop_set_drive_err(flash_dev, "drive", 661 blk_by_legacy_dinfo(dinfo), 662 &error_fatal); 663 } 664 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); 665 666 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 667 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); 668 669 /* Connect an SD card to SPI2 */ 670 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); 671 672 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); 673 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); 674 675 dinfo = drive_get(IF_SD, 0, 0); 676 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 677 card_dev = qdev_new(TYPE_SD_CARD); 678 qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); 679 qdev_prop_set_bit(card_dev, "spi", true); 680 qdev_realize_and_unref(card_dev, 681 qdev_get_child_bus(sd_dev, "sd-bus"), 682 &error_fatal); 683 } 684 685 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 686 { 687 SiFiveUState *s = RISCV_U_MACHINE(obj); 688 689 return s->start_in_flash; 690 } 691 692 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 693 { 694 SiFiveUState *s = RISCV_U_MACHINE(obj); 695 696 s->start_in_flash = value; 697 } 698 699 static void sifive_u_machine_instance_init(Object *obj) 700 { 701 SiFiveUState *s = RISCV_U_MACHINE(obj); 702 703 s->start_in_flash = false; 704 s->msel = 0; 705 object_property_add_uint32_ptr(obj, "msel", &s->msel, 706 OBJ_PROP_FLAG_READWRITE); 707 object_property_set_description(obj, "msel", 708 "Mode Select (MSEL[3:0]) pin state"); 709 710 s->serial = OTP_SERIAL; 711 object_property_add_uint32_ptr(obj, "serial", &s->serial, 712 OBJ_PROP_FLAG_READWRITE); 713 object_property_set_description(obj, "serial", "Board serial number"); 714 } 715 716 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 717 { 718 MachineClass *mc = MACHINE_CLASS(oc); 719 720 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 721 mc->init = sifive_u_machine_init; 722 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 723 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 724 mc->default_cpu_type = SIFIVE_U_CPU; 725 mc->default_cpus = mc->min_cpus; 726 mc->default_ram_id = "riscv.sifive.u.ram"; 727 728 object_class_property_add_bool(oc, "start-in-flash", 729 sifive_u_machine_get_start_in_flash, 730 sifive_u_machine_set_start_in_flash); 731 object_class_property_set_description(oc, "start-in-flash", 732 "Set on to tell QEMU's ROM to jump to " 733 "flash. Otherwise QEMU will jump to DRAM " 734 "or L2LIM depending on the msel value"); 735 } 736 737 static const TypeInfo sifive_u_machine_typeinfo = { 738 .name = MACHINE_TYPE_NAME("sifive_u"), 739 .parent = TYPE_MACHINE, 740 .class_init = sifive_u_machine_class_init, 741 .instance_init = sifive_u_machine_instance_init, 742 .instance_size = sizeof(SiFiveUState), 743 }; 744 745 static void sifive_u_machine_init_register_types(void) 746 { 747 type_register_static(&sifive_u_machine_typeinfo); 748 } 749 750 type_init(sifive_u_machine_init_register_types) 751 752 static void sifive_u_soc_instance_init(Object *obj) 753 { 754 SiFiveUSoCState *s = RISCV_U_SOC(obj); 755 756 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 757 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 758 759 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 760 TYPE_RISCV_HART_ARRAY); 761 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 762 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 763 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 764 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 765 766 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 767 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 768 769 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 770 TYPE_RISCV_HART_ARRAY); 771 772 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 773 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 774 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 775 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 776 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 777 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); 778 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); 779 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); 780 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); 781 } 782 783 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 784 { 785 MachineState *ms = MACHINE(qdev_get_machine()); 786 SiFiveUSoCState *s = RISCV_U_SOC(dev); 787 const MemMapEntry *memmap = sifive_u_memmap; 788 MemoryRegion *system_memory = get_system_memory(); 789 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 790 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 791 char *plic_hart_config; 792 int i, j; 793 NICInfo *nd = &nd_table[0]; 794 795 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 796 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 797 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 798 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 799 800 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); 801 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); 802 /* 803 * The cluster must be realized after the RISC-V hart array container, 804 * as the container's CPU object is only created on realize, and the 805 * CPU must exist and have been parented into the cluster before the 806 * cluster is realized. 807 */ 808 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 809 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 810 811 /* boot rom */ 812 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 813 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 814 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 815 mask_rom); 816 817 /* 818 * Add L2-LIM at reset size. 819 * This should be reduced in size as the L2 Cache Controller WayEnable 820 * register is incremented. Unfortunately I don't see a nice (or any) way 821 * to handle reducing or blocking out the L2 LIM while still allowing it 822 * be re returned to all enabled after a reset. For the time being, just 823 * leave it enabled all the time. This won't break anything, but will be 824 * too generous to misbehaving guests. 825 */ 826 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 827 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 828 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 829 l2lim_mem); 830 831 /* create PLIC hart topology configuration string */ 832 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); 833 834 /* MMIO */ 835 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 836 plic_hart_config, ms->smp.cpus, 0, 837 SIFIVE_U_PLIC_NUM_SOURCES, 838 SIFIVE_U_PLIC_NUM_PRIORITIES, 839 SIFIVE_U_PLIC_PRIORITY_BASE, 840 SIFIVE_U_PLIC_PENDING_BASE, 841 SIFIVE_U_PLIC_ENABLE_BASE, 842 SIFIVE_U_PLIC_ENABLE_STRIDE, 843 SIFIVE_U_PLIC_CONTEXT_BASE, 844 SIFIVE_U_PLIC_CONTEXT_STRIDE, 845 memmap[SIFIVE_U_DEV_PLIC].size); 846 g_free(plic_hart_config); 847 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 848 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 849 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 850 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 851 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, 852 ms->smp.cpus, false); 853 riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + 854 RISCV_ACLINT_SWI_SIZE, 855 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 856 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 857 CLINT_TIMEBASE_FREQ, false); 858 859 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 860 return; 861 } 862 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 863 864 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 865 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 866 return; 867 } 868 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 869 870 /* Pass all GPIOs to the SOC layer so they are available to the board */ 871 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 872 873 /* Connect GPIO interrupts to the PLIC */ 874 for (i = 0; i < 16; i++) { 875 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 876 qdev_get_gpio_in(DEVICE(s->plic), 877 SIFIVE_U_GPIO_IRQ0 + i)); 878 } 879 880 /* PDMA */ 881 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 882 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 883 884 /* Connect PDMA interrupts to the PLIC */ 885 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 886 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 887 qdev_get_gpio_in(DEVICE(s->plic), 888 SIFIVE_U_PDMA_IRQ0 + i)); 889 } 890 891 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 892 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 893 return; 894 } 895 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 896 897 /* FIXME use qdev NIC properties instead of nd_table[] */ 898 if (nd->used) { 899 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 900 qdev_set_nic_properties(DEVICE(&s->gem), nd); 901 } 902 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 903 &error_abort); 904 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 905 return; 906 } 907 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 908 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 909 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 910 911 /* PWM */ 912 for (i = 0; i < 2; i++) { 913 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { 914 return; 915 } 916 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, 917 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); 918 919 /* Connect PWM interrupts to the PLIC */ 920 for (j = 0; j < SIFIVE_PWM_IRQS; j++) { 921 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, 922 qdev_get_gpio_in(DEVICE(s->plic), 923 SIFIVE_U_PWM0_IRQ0 + (i * 4) + j)); 924 } 925 } 926 927 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 928 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 929 930 create_unimplemented_device("riscv.sifive.u.dmc", 931 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 932 933 create_unimplemented_device("riscv.sifive.u.l2cc", 934 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 935 936 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); 937 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, 938 memmap[SIFIVE_U_DEV_QSPI0].base); 939 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, 940 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); 941 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); 942 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, 943 memmap[SIFIVE_U_DEV_QSPI2].base); 944 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, 945 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); 946 } 947 948 static Property sifive_u_soc_props[] = { 949 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 950 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 951 DEFINE_PROP_END_OF_LIST() 952 }; 953 954 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 955 { 956 DeviceClass *dc = DEVICE_CLASS(oc); 957 958 device_class_set_props(dc, sifive_u_soc_props); 959 dc->realize = sifive_u_soc_realize; 960 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 961 dc->user_creatable = false; 962 } 963 964 static const TypeInfo sifive_u_soc_type_info = { 965 .name = TYPE_RISCV_U_SOC, 966 .parent = TYPE_DEVICE, 967 .instance_size = sizeof(SiFiveUSoCState), 968 .instance_init = sifive_u_soc_instance_init, 969 .class_init = sifive_u_soc_class_init, 970 }; 971 972 static void sifive_u_soc_register_types(void) 973 { 974 type_register_static(&sifive_u_soc_type_info); 975 } 976 977 type_init(sifive_u_soc_register_types) 978