1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 19 * This board currently generates devicetree dynamically that indicates at least 20 * two harts and up to five harts. 21 * 22 * This program is free software; you can redistribute it and/or modify it 23 * under the terms and conditions of the GNU General Public License, 24 * version 2 or later, as published by the Free Software Foundation. 25 * 26 * This program is distributed in the hope it will be useful, but WITHOUT 27 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 28 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 29 * more details. 30 * 31 * You should have received a copy of the GNU General Public License along with 32 * this program. If not, see <http://www.gnu.org/licenses/>. 33 */ 34 35 #include "qemu/osdep.h" 36 #include "qemu/log.h" 37 #include "qemu/error-report.h" 38 #include "qapi/error.h" 39 #include "qapi/visitor.h" 40 #include "hw/boards.h" 41 #include "hw/irq.h" 42 #include "hw/loader.h" 43 #include "hw/sysbus.h" 44 #include "hw/char/serial.h" 45 #include "hw/cpu/cluster.h" 46 #include "hw/misc/unimp.h" 47 #include "target/riscv/cpu.h" 48 #include "hw/riscv/riscv_hart.h" 49 #include "hw/riscv/sifive_u.h" 50 #include "hw/riscv/boot.h" 51 #include "hw/char/sifive_uart.h" 52 #include "hw/intc/sifive_clint.h" 53 #include "hw/intc/sifive_plic.h" 54 #include "chardev/char.h" 55 #include "net/eth.h" 56 #include "sysemu/arch_init.h" 57 #include "sysemu/device_tree.h" 58 #include "sysemu/runstate.h" 59 #include "sysemu/sysemu.h" 60 61 #include <libfdt.h> 62 63 #if defined(TARGET_RISCV32) 64 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" 65 #else 66 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" 67 #endif 68 69 static const struct MemmapEntry { 70 hwaddr base; 71 hwaddr size; 72 } sifive_u_memmap[] = { 73 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 74 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 75 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 76 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 77 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 78 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 79 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 80 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 81 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 82 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 83 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 84 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 85 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 86 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 87 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 88 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 89 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 90 }; 91 92 #define OTP_SERIAL 1 93 #define GEM_REVISION 0x10070109 94 95 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 96 uint64_t mem_size, const char *cmdline) 97 { 98 MachineState *ms = MACHINE(qdev_get_machine()); 99 void *fdt; 100 int cpu; 101 uint32_t *cells; 102 char *nodename; 103 char ethclk_names[] = "pclk\0hclk"; 104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 105 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 106 107 if (ms->dtb) { 108 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); 109 if (!fdt) { 110 error_report("load_device_tree() failed"); 111 exit(1); 112 } 113 goto update_bootargs; 114 } else { 115 fdt = s->fdt = create_device_tree(&s->fdt_size); 116 if (!fdt) { 117 error_report("create_device_tree() failed"); 118 exit(1); 119 } 120 } 121 122 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 123 qemu_fdt_setprop_string(fdt, "/", "compatible", 124 "sifive,hifive-unleashed-a00"); 125 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 126 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 127 128 qemu_fdt_add_subnode(fdt, "/soc"); 129 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 130 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 131 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 132 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 133 134 hfclk_phandle = phandle++; 135 nodename = g_strdup_printf("/hfclk"); 136 qemu_fdt_add_subnode(fdt, nodename); 137 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 138 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 139 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 140 SIFIVE_U_HFCLK_FREQ); 141 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 142 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 143 g_free(nodename); 144 145 rtcclk_phandle = phandle++; 146 nodename = g_strdup_printf("/rtcclk"); 147 qemu_fdt_add_subnode(fdt, nodename); 148 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 149 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 150 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 151 SIFIVE_U_RTCCLK_FREQ); 152 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 153 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 154 g_free(nodename); 155 156 nodename = g_strdup_printf("/memory@%lx", 157 (long)memmap[SIFIVE_U_DEV_DRAM].base); 158 qemu_fdt_add_subnode(fdt, nodename); 159 qemu_fdt_setprop_cells(fdt, nodename, "reg", 160 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 161 mem_size >> 32, mem_size); 162 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 163 g_free(nodename); 164 165 qemu_fdt_add_subnode(fdt, "/cpus"); 166 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 167 SIFIVE_CLINT_TIMEBASE_FREQ); 168 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 169 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 170 171 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 172 int cpu_phandle = phandle++; 173 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 174 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 175 char *isa; 176 qemu_fdt_add_subnode(fdt, nodename); 177 /* cpu 0 is the management hart that does not have mmu */ 178 if (cpu != 0) { 179 #if defined(TARGET_RISCV32) 180 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 181 #else 182 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 183 #endif 184 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 185 } else { 186 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 187 } 188 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 189 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 190 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 191 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 192 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 193 qemu_fdt_add_subnode(fdt, intc); 194 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 195 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 196 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 197 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 198 g_free(isa); 199 g_free(intc); 200 g_free(nodename); 201 } 202 203 cells = g_new0(uint32_t, ms->smp.cpus * 4); 204 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 205 nodename = 206 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 207 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 208 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 209 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 210 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 211 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 212 g_free(nodename); 213 } 214 nodename = g_strdup_printf("/soc/clint@%lx", 215 (long)memmap[SIFIVE_U_DEV_CLINT].base); 216 qemu_fdt_add_subnode(fdt, nodename); 217 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 218 qemu_fdt_setprop_cells(fdt, nodename, "reg", 219 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 220 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 221 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 222 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 223 g_free(cells); 224 g_free(nodename); 225 226 nodename = g_strdup_printf("/soc/otp@%lx", 227 (long)memmap[SIFIVE_U_DEV_OTP].base); 228 qemu_fdt_add_subnode(fdt, nodename); 229 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 230 qemu_fdt_setprop_cells(fdt, nodename, "reg", 231 0x0, memmap[SIFIVE_U_DEV_OTP].base, 232 0x0, memmap[SIFIVE_U_DEV_OTP].size); 233 qemu_fdt_setprop_string(fdt, nodename, "compatible", 234 "sifive,fu540-c000-otp"); 235 g_free(nodename); 236 237 prci_phandle = phandle++; 238 nodename = g_strdup_printf("/soc/clock-controller@%lx", 239 (long)memmap[SIFIVE_U_DEV_PRCI].base); 240 qemu_fdt_add_subnode(fdt, nodename); 241 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 242 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 243 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 244 hfclk_phandle, rtcclk_phandle); 245 qemu_fdt_setprop_cells(fdt, nodename, "reg", 246 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 247 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 248 qemu_fdt_setprop_string(fdt, nodename, "compatible", 249 "sifive,fu540-c000-prci"); 250 g_free(nodename); 251 252 plic_phandle = phandle++; 253 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 254 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 255 nodename = 256 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 257 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 258 /* cpu 0 is the management hart that does not have S-mode */ 259 if (cpu == 0) { 260 cells[0] = cpu_to_be32(intc_phandle); 261 cells[1] = cpu_to_be32(IRQ_M_EXT); 262 } else { 263 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 264 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 265 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 266 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 267 } 268 g_free(nodename); 269 } 270 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 271 (long)memmap[SIFIVE_U_DEV_PLIC].base); 272 qemu_fdt_add_subnode(fdt, nodename); 273 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 274 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 275 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 276 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 277 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 278 qemu_fdt_setprop_cells(fdt, nodename, "reg", 279 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 280 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 281 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 282 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 283 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 284 g_free(cells); 285 g_free(nodename); 286 287 gpio_phandle = phandle++; 288 nodename = g_strdup_printf("/soc/gpio@%lx", 289 (long)memmap[SIFIVE_U_DEV_GPIO].base); 290 qemu_fdt_add_subnode(fdt, nodename); 291 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 292 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 293 prci_phandle, PRCI_CLK_TLCLK); 294 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 295 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 296 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 297 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 298 qemu_fdt_setprop_cells(fdt, nodename, "reg", 299 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 300 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 301 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 302 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 303 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 304 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 305 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 306 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 307 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 308 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 309 g_free(nodename); 310 311 nodename = g_strdup_printf("/gpio-restart"); 312 qemu_fdt_add_subnode(fdt, nodename); 313 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 314 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 315 g_free(nodename); 316 317 nodename = g_strdup_printf("/soc/dma@%lx", 318 (long)memmap[SIFIVE_U_DEV_PDMA].base); 319 qemu_fdt_add_subnode(fdt, nodename); 320 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 321 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 322 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 323 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 324 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 325 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 326 qemu_fdt_setprop_cells(fdt, nodename, "reg", 327 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 328 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 329 qemu_fdt_setprop_string(fdt, nodename, "compatible", 330 "sifive,fu540-c000-pdma"); 331 g_free(nodename); 332 333 nodename = g_strdup_printf("/soc/cache-controller@%lx", 334 (long)memmap[SIFIVE_U_DEV_L2CC].base); 335 qemu_fdt_add_subnode(fdt, nodename); 336 qemu_fdt_setprop_cells(fdt, nodename, "reg", 337 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 338 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 339 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 340 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 341 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 342 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 343 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 344 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 345 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 346 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 347 qemu_fdt_setprop_string(fdt, nodename, "compatible", 348 "sifive,fu540-c000-ccache"); 349 g_free(nodename); 350 351 phy_phandle = phandle++; 352 nodename = g_strdup_printf("/soc/ethernet@%lx", 353 (long)memmap[SIFIVE_U_DEV_GEM].base); 354 qemu_fdt_add_subnode(fdt, nodename); 355 qemu_fdt_setprop_string(fdt, nodename, "compatible", 356 "sifive,fu540-c000-gem"); 357 qemu_fdt_setprop_cells(fdt, nodename, "reg", 358 0x0, memmap[SIFIVE_U_DEV_GEM].base, 359 0x0, memmap[SIFIVE_U_DEV_GEM].size, 360 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 361 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 362 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 363 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 364 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 365 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 366 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 367 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 368 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 369 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 370 sizeof(ethclk_names)); 371 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 372 s->soc.gem.conf.macaddr.a, ETH_ALEN); 373 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 374 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 375 376 qemu_fdt_add_subnode(fdt, "/aliases"); 377 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 378 379 g_free(nodename); 380 381 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 382 (long)memmap[SIFIVE_U_DEV_GEM].base); 383 qemu_fdt_add_subnode(fdt, nodename); 384 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 385 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 386 g_free(nodename); 387 388 nodename = g_strdup_printf("/soc/serial@%lx", 389 (long)memmap[SIFIVE_U_DEV_UART0].base); 390 qemu_fdt_add_subnode(fdt, nodename); 391 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 392 qemu_fdt_setprop_cells(fdt, nodename, "reg", 393 0x0, memmap[SIFIVE_U_DEV_UART0].base, 394 0x0, memmap[SIFIVE_U_DEV_UART0].size); 395 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 396 prci_phandle, PRCI_CLK_TLCLK); 397 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 398 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 399 400 qemu_fdt_add_subnode(fdt, "/chosen"); 401 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 402 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 403 404 g_free(nodename); 405 406 update_bootargs: 407 if (cmdline) { 408 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 409 } 410 } 411 412 static void sifive_u_machine_reset(void *opaque, int n, int level) 413 { 414 /* gpio pin active low triggers reset */ 415 if (!level) { 416 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 417 } 418 } 419 420 static void sifive_u_machine_init(MachineState *machine) 421 { 422 const struct MemmapEntry *memmap = sifive_u_memmap; 423 SiFiveUState *s = RISCV_U_MACHINE(machine); 424 MemoryRegion *system_memory = get_system_memory(); 425 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 426 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 427 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 428 target_ulong firmware_end_addr, kernel_start_addr; 429 uint32_t start_addr_hi32 = 0x00000000; 430 int i; 431 uint32_t fdt_load_addr; 432 uint64_t kernel_entry; 433 434 /* Initialize SoC */ 435 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 436 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 437 &error_abort); 438 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 439 &error_abort); 440 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 441 442 /* register RAM */ 443 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 444 machine->ram_size, &error_fatal); 445 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 446 main_mem); 447 448 /* register QSPI0 Flash */ 449 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 450 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 451 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 452 flash0); 453 454 /* register gpio-restart */ 455 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 456 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 457 458 /* create device tree */ 459 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 460 461 if (s->start_in_flash) { 462 /* 463 * If start_in_flash property is given, assign s->msel to a value 464 * that representing booting from QSPI0 memory-mapped flash. 465 * 466 * This also means that when both start_in_flash and msel properties 467 * are given, start_in_flash takes the precedence over msel. 468 * 469 * Note this is to keep backward compatibility not to break existing 470 * users that use start_in_flash property. 471 */ 472 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 473 } 474 475 switch (s->msel) { 476 case MSEL_MEMMAP_QSPI0_FLASH: 477 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 478 break; 479 case MSEL_L2LIM_QSPI0_FLASH: 480 case MSEL_L2LIM_QSPI2_SD: 481 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 482 break; 483 default: 484 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 485 break; 486 } 487 488 firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, 489 start_addr, NULL); 490 491 if (machine->kernel_filename) { 492 kernel_start_addr = riscv_calc_kernel_start_addr(machine, 493 firmware_end_addr); 494 495 kernel_entry = riscv_load_kernel(machine->kernel_filename, 496 kernel_start_addr, NULL); 497 498 if (machine->initrd_filename) { 499 hwaddr start; 500 hwaddr end = riscv_load_initrd(machine->initrd_filename, 501 machine->ram_size, kernel_entry, 502 &start); 503 qemu_fdt_setprop_cell(s->fdt, "/chosen", 504 "linux,initrd-start", start); 505 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 506 end); 507 } 508 } else { 509 /* 510 * If dynamic firmware is used, it doesn't know where is the next mode 511 * if kernel argument is not set. 512 */ 513 kernel_entry = 0; 514 } 515 516 /* Compute the fdt load address in dram */ 517 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, 518 machine->ram_size, s->fdt); 519 #if defined(TARGET_RISCV64) 520 start_addr_hi32 = start_addr >> 32; 521 #endif 522 523 /* reset vector */ 524 uint32_t reset_vec[11] = { 525 s->msel, /* MSEL pin state */ 526 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 527 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 528 0xf1402573, /* csrr a0, mhartid */ 529 #if defined(TARGET_RISCV32) 530 0x0202a583, /* lw a1, 32(t0) */ 531 0x0182a283, /* lw t0, 24(t0) */ 532 #elif defined(TARGET_RISCV64) 533 0x0202b583, /* ld a1, 32(t0) */ 534 0x0182b283, /* ld t0, 24(t0) */ 535 #endif 536 0x00028067, /* jr t0 */ 537 start_addr, /* start: .dword */ 538 start_addr_hi32, 539 fdt_load_addr, /* fdt_laddr: .dword */ 540 0x00000000, 541 /* fw_dyn: */ 542 }; 543 544 /* copy in the reset vector in little_endian byte order */ 545 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 546 reset_vec[i] = cpu_to_le32(reset_vec[i]); 547 } 548 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 549 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 550 551 riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base, 552 memmap[SIFIVE_U_DEV_MROM].size, 553 sizeof(reset_vec), kernel_entry); 554 } 555 556 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 557 { 558 SiFiveUState *s = RISCV_U_MACHINE(obj); 559 560 return s->start_in_flash; 561 } 562 563 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 564 { 565 SiFiveUState *s = RISCV_U_MACHINE(obj); 566 567 s->start_in_flash = value; 568 } 569 570 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 571 const char *name, void *opaque, 572 Error **errp) 573 { 574 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 575 } 576 577 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 578 const char *name, void *opaque, 579 Error **errp) 580 { 581 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 582 } 583 584 static void sifive_u_machine_instance_init(Object *obj) 585 { 586 SiFiveUState *s = RISCV_U_MACHINE(obj); 587 588 s->start_in_flash = false; 589 s->msel = 0; 590 object_property_add(obj, "msel", "uint32", 591 sifive_u_machine_get_uint32_prop, 592 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 593 object_property_set_description(obj, "msel", 594 "Mode Select (MSEL[3:0]) pin state"); 595 596 s->serial = OTP_SERIAL; 597 object_property_add(obj, "serial", "uint32", 598 sifive_u_machine_get_uint32_prop, 599 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 600 object_property_set_description(obj, "serial", "Board serial number"); 601 } 602 603 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 604 { 605 MachineClass *mc = MACHINE_CLASS(oc); 606 607 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 608 mc->init = sifive_u_machine_init; 609 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 610 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 611 #if defined(TARGET_RISCV32) 612 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; 613 #elif defined(TARGET_RISCV64) 614 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; 615 #endif 616 mc->default_cpus = mc->min_cpus; 617 618 object_class_property_add_bool(oc, "start-in-flash", 619 sifive_u_machine_get_start_in_flash, 620 sifive_u_machine_set_start_in_flash); 621 object_class_property_set_description(oc, "start-in-flash", 622 "Set on to tell QEMU's ROM to jump to " 623 "flash. Otherwise QEMU will jump to DRAM " 624 "or L2LIM depending on the msel value"); 625 } 626 627 static const TypeInfo sifive_u_machine_typeinfo = { 628 .name = MACHINE_TYPE_NAME("sifive_u"), 629 .parent = TYPE_MACHINE, 630 .class_init = sifive_u_machine_class_init, 631 .instance_init = sifive_u_machine_instance_init, 632 .instance_size = sizeof(SiFiveUState), 633 }; 634 635 static void sifive_u_machine_init_register_types(void) 636 { 637 type_register_static(&sifive_u_machine_typeinfo); 638 } 639 640 type_init(sifive_u_machine_init_register_types) 641 642 static void sifive_u_soc_instance_init(Object *obj) 643 { 644 SiFiveUSoCState *s = RISCV_U_SOC(obj); 645 646 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 647 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 648 649 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 650 TYPE_RISCV_HART_ARRAY); 651 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 652 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 653 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 654 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 655 656 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 657 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 658 659 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 660 TYPE_RISCV_HART_ARRAY); 661 662 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 663 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 664 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 665 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 666 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 667 } 668 669 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 670 { 671 MachineState *ms = MACHINE(qdev_get_machine()); 672 SiFiveUSoCState *s = RISCV_U_SOC(dev); 673 const struct MemmapEntry *memmap = sifive_u_memmap; 674 MemoryRegion *system_memory = get_system_memory(); 675 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 676 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 677 char *plic_hart_config; 678 size_t plic_hart_config_len; 679 int i; 680 NICInfo *nd = &nd_table[0]; 681 682 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 683 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 684 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 685 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 686 687 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 688 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 689 /* 690 * The cluster must be realized after the RISC-V hart array container, 691 * as the container's CPU object is only created on realize, and the 692 * CPU must exist and have been parented into the cluster before the 693 * cluster is realized. 694 */ 695 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 696 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 697 698 /* boot rom */ 699 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 700 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 701 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 702 mask_rom); 703 704 /* 705 * Add L2-LIM at reset size. 706 * This should be reduced in size as the L2 Cache Controller WayEnable 707 * register is incremented. Unfortunately I don't see a nice (or any) way 708 * to handle reducing or blocking out the L2 LIM while still allowing it 709 * be re returned to all enabled after a reset. For the time being, just 710 * leave it enabled all the time. This won't break anything, but will be 711 * too generous to misbehaving guests. 712 */ 713 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 714 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 715 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 716 l2lim_mem); 717 718 /* create PLIC hart topology configuration string */ 719 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 720 ms->smp.cpus; 721 plic_hart_config = g_malloc0(plic_hart_config_len); 722 for (i = 0; i < ms->smp.cpus; i++) { 723 if (i != 0) { 724 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 725 plic_hart_config_len); 726 } else { 727 strncat(plic_hart_config, "M", plic_hart_config_len); 728 } 729 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 730 } 731 732 /* MMIO */ 733 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 734 plic_hart_config, 0, 735 SIFIVE_U_PLIC_NUM_SOURCES, 736 SIFIVE_U_PLIC_NUM_PRIORITIES, 737 SIFIVE_U_PLIC_PRIORITY_BASE, 738 SIFIVE_U_PLIC_PENDING_BASE, 739 SIFIVE_U_PLIC_ENABLE_BASE, 740 SIFIVE_U_PLIC_ENABLE_STRIDE, 741 SIFIVE_U_PLIC_CONTEXT_BASE, 742 SIFIVE_U_PLIC_CONTEXT_STRIDE, 743 memmap[SIFIVE_U_DEV_PLIC].size); 744 g_free(plic_hart_config); 745 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 746 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 747 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 748 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 749 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, 750 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, 751 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 752 SIFIVE_CLINT_TIMEBASE_FREQ, false); 753 754 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 755 return; 756 } 757 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 758 759 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 760 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 761 return; 762 } 763 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 764 765 /* Pass all GPIOs to the SOC layer so they are available to the board */ 766 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 767 768 /* Connect GPIO interrupts to the PLIC */ 769 for (i = 0; i < 16; i++) { 770 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 771 qdev_get_gpio_in(DEVICE(s->plic), 772 SIFIVE_U_GPIO_IRQ0 + i)); 773 } 774 775 /* PDMA */ 776 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 777 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 778 779 /* Connect PDMA interrupts to the PLIC */ 780 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 781 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 782 qdev_get_gpio_in(DEVICE(s->plic), 783 SIFIVE_U_PDMA_IRQ0 + i)); 784 } 785 786 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 787 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 788 return; 789 } 790 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 791 792 /* FIXME use qdev NIC properties instead of nd_table[] */ 793 if (nd->used) { 794 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 795 qdev_set_nic_properties(DEVICE(&s->gem), nd); 796 } 797 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 798 &error_abort); 799 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 800 return; 801 } 802 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 803 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 804 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 805 806 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 807 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 808 809 create_unimplemented_device("riscv.sifive.u.dmc", 810 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 811 812 create_unimplemented_device("riscv.sifive.u.l2cc", 813 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 814 } 815 816 static Property sifive_u_soc_props[] = { 817 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 818 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 819 DEFINE_PROP_END_OF_LIST() 820 }; 821 822 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 823 { 824 DeviceClass *dc = DEVICE_CLASS(oc); 825 826 device_class_set_props(dc, sifive_u_soc_props); 827 dc->realize = sifive_u_soc_realize; 828 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 829 dc->user_creatable = false; 830 } 831 832 static const TypeInfo sifive_u_soc_type_info = { 833 .name = TYPE_RISCV_U_SOC, 834 .parent = TYPE_DEVICE, 835 .instance_size = sizeof(SiFiveUSoCState), 836 .instance_init = sifive_u_soc_instance_init, 837 .class_init = sifive_u_soc_class_init, 838 }; 839 840 static void sifive_u_soc_register_types(void) 841 { 842 type_register_static(&sifive_u_soc_type_info); 843 } 844 845 type_init(sifive_u_soc_register_types) 846