1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) OTP (One-Time Programmable) memory with stored serial number 15 * 5) GEM (Gigabit Ethernet Controller) and management block 16 * 17 * This board currently generates devicetree dynamically that indicates at least 18 * two harts and up to five harts. 19 * 20 * This program is free software; you can redistribute it and/or modify it 21 * under the terms and conditions of the GNU General Public License, 22 * version 2 or later, as published by the Free Software Foundation. 23 * 24 * This program is distributed in the hope it will be useful, but WITHOUT 25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 27 * more details. 28 * 29 * You should have received a copy of the GNU General Public License along with 30 * this program. If not, see <http://www.gnu.org/licenses/>. 31 */ 32 33 #include "qemu/osdep.h" 34 #include "qemu/log.h" 35 #include "qemu/error-report.h" 36 #include "qapi/error.h" 37 #include "hw/boards.h" 38 #include "hw/loader.h" 39 #include "hw/sysbus.h" 40 #include "hw/char/serial.h" 41 #include "hw/cpu/cluster.h" 42 #include "hw/misc/unimp.h" 43 #include "target/riscv/cpu.h" 44 #include "hw/riscv/riscv_hart.h" 45 #include "hw/riscv/sifive_plic.h" 46 #include "hw/riscv/sifive_clint.h" 47 #include "hw/riscv/sifive_uart.h" 48 #include "hw/riscv/sifive_u.h" 49 #include "hw/riscv/boot.h" 50 #include "chardev/char.h" 51 #include "net/eth.h" 52 #include "sysemu/arch_init.h" 53 #include "sysemu/device_tree.h" 54 #include "sysemu/sysemu.h" 55 #include "exec/address-spaces.h" 56 57 #include <libfdt.h> 58 59 #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" 60 61 static const struct MemmapEntry { 62 hwaddr base; 63 hwaddr size; 64 } sifive_u_memmap[] = { 65 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 66 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 67 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 68 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 69 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, 70 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, 71 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, 72 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, 73 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 74 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, 75 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, 76 }; 77 78 #define OTP_SERIAL 1 79 #define GEM_REVISION 0x10070109 80 81 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 82 uint64_t mem_size, const char *cmdline) 83 { 84 MachineState *ms = MACHINE(qdev_get_machine()); 85 void *fdt; 86 int cpu; 87 uint32_t *cells; 88 char *nodename; 89 char ethclk_names[] = "pclk\0hclk"; 90 uint32_t plic_phandle, prci_phandle, phandle = 1; 91 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 92 93 fdt = s->fdt = create_device_tree(&s->fdt_size); 94 if (!fdt) { 95 error_report("create_device_tree() failed"); 96 exit(1); 97 } 98 99 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 100 qemu_fdt_setprop_string(fdt, "/", "compatible", 101 "sifive,hifive-unleashed-a00"); 102 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 103 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 104 105 qemu_fdt_add_subnode(fdt, "/soc"); 106 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 107 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 108 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 109 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 110 111 hfclk_phandle = phandle++; 112 nodename = g_strdup_printf("/hfclk"); 113 qemu_fdt_add_subnode(fdt, nodename); 114 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 115 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 116 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 117 SIFIVE_U_HFCLK_FREQ); 118 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 119 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 120 g_free(nodename); 121 122 rtcclk_phandle = phandle++; 123 nodename = g_strdup_printf("/rtcclk"); 124 qemu_fdt_add_subnode(fdt, nodename); 125 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 126 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 127 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 128 SIFIVE_U_RTCCLK_FREQ); 129 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 130 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 131 g_free(nodename); 132 133 nodename = g_strdup_printf("/memory@%lx", 134 (long)memmap[SIFIVE_U_DRAM].base); 135 qemu_fdt_add_subnode(fdt, nodename); 136 qemu_fdt_setprop_cells(fdt, nodename, "reg", 137 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 138 mem_size >> 32, mem_size); 139 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 140 g_free(nodename); 141 142 qemu_fdt_add_subnode(fdt, "/cpus"); 143 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 144 SIFIVE_CLINT_TIMEBASE_FREQ); 145 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 146 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 147 148 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 149 int cpu_phandle = phandle++; 150 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 151 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 152 char *isa; 153 qemu_fdt_add_subnode(fdt, nodename); 154 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 155 SIFIVE_U_CLOCK_FREQ); 156 /* cpu 0 is the management hart that does not have mmu */ 157 if (cpu != 0) { 158 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 159 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 160 } else { 161 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 162 } 163 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 164 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 165 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 166 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 167 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 168 qemu_fdt_add_subnode(fdt, intc); 169 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 170 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 171 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 172 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 173 g_free(isa); 174 g_free(intc); 175 g_free(nodename); 176 } 177 178 cells = g_new0(uint32_t, ms->smp.cpus * 4); 179 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 180 nodename = 181 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 182 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 183 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 184 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 185 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 186 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 187 g_free(nodename); 188 } 189 nodename = g_strdup_printf("/soc/clint@%lx", 190 (long)memmap[SIFIVE_U_CLINT].base); 191 qemu_fdt_add_subnode(fdt, nodename); 192 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 193 qemu_fdt_setprop_cells(fdt, nodename, "reg", 194 0x0, memmap[SIFIVE_U_CLINT].base, 195 0x0, memmap[SIFIVE_U_CLINT].size); 196 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 197 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 198 g_free(cells); 199 g_free(nodename); 200 201 prci_phandle = phandle++; 202 nodename = g_strdup_printf("/soc/clock-controller@%lx", 203 (long)memmap[SIFIVE_U_PRCI].base); 204 qemu_fdt_add_subnode(fdt, nodename); 205 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 206 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 207 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 208 hfclk_phandle, rtcclk_phandle); 209 qemu_fdt_setprop_cells(fdt, nodename, "reg", 210 0x0, memmap[SIFIVE_U_PRCI].base, 211 0x0, memmap[SIFIVE_U_PRCI].size); 212 qemu_fdt_setprop_string(fdt, nodename, "compatible", 213 "sifive,fu540-c000-prci"); 214 g_free(nodename); 215 216 plic_phandle = phandle++; 217 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 218 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 219 nodename = 220 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 221 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 222 /* cpu 0 is the management hart that does not have S-mode */ 223 if (cpu == 0) { 224 cells[0] = cpu_to_be32(intc_phandle); 225 cells[1] = cpu_to_be32(IRQ_M_EXT); 226 } else { 227 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 228 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 229 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 230 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 231 } 232 g_free(nodename); 233 } 234 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 235 (long)memmap[SIFIVE_U_PLIC].base); 236 qemu_fdt_add_subnode(fdt, nodename); 237 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 238 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 239 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 240 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 241 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 242 qemu_fdt_setprop_cells(fdt, nodename, "reg", 243 0x0, memmap[SIFIVE_U_PLIC].base, 244 0x0, memmap[SIFIVE_U_PLIC].size); 245 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 246 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 247 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 248 g_free(cells); 249 g_free(nodename); 250 251 phy_phandle = phandle++; 252 nodename = g_strdup_printf("/soc/ethernet@%lx", 253 (long)memmap[SIFIVE_U_GEM].base); 254 qemu_fdt_add_subnode(fdt, nodename); 255 qemu_fdt_setprop_string(fdt, nodename, "compatible", 256 "sifive,fu540-c000-gem"); 257 qemu_fdt_setprop_cells(fdt, nodename, "reg", 258 0x0, memmap[SIFIVE_U_GEM].base, 259 0x0, memmap[SIFIVE_U_GEM].size, 260 0x0, memmap[SIFIVE_U_GEM_MGMT].base, 261 0x0, memmap[SIFIVE_U_GEM_MGMT].size); 262 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 263 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 264 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 265 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 266 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 267 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 268 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 269 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 270 sizeof(ethclk_names)); 271 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 272 s->soc.gem.conf.macaddr.a, ETH_ALEN); 273 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 274 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 275 g_free(nodename); 276 277 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 278 (long)memmap[SIFIVE_U_GEM].base); 279 qemu_fdt_add_subnode(fdt, nodename); 280 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 281 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 282 g_free(nodename); 283 284 nodename = g_strdup_printf("/soc/serial@%lx", 285 (long)memmap[SIFIVE_U_UART0].base); 286 qemu_fdt_add_subnode(fdt, nodename); 287 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 288 qemu_fdt_setprop_cells(fdt, nodename, "reg", 289 0x0, memmap[SIFIVE_U_UART0].base, 290 0x0, memmap[SIFIVE_U_UART0].size); 291 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 292 prci_phandle, PRCI_CLK_TLCLK); 293 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 294 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 295 296 qemu_fdt_add_subnode(fdt, "/chosen"); 297 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 298 if (cmdline) { 299 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 300 } 301 302 qemu_fdt_add_subnode(fdt, "/aliases"); 303 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 304 305 g_free(nodename); 306 } 307 308 static void riscv_sifive_u_init(MachineState *machine) 309 { 310 const struct MemmapEntry *memmap = sifive_u_memmap; 311 312 SiFiveUState *s = g_new0(SiFiveUState, 1); 313 MemoryRegion *system_memory = get_system_memory(); 314 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 315 int i; 316 317 /* Initialize SoC */ 318 object_initialize_child(OBJECT(machine), "soc", &s->soc, 319 sizeof(s->soc), TYPE_RISCV_U_SOC, 320 &error_abort, NULL); 321 object_property_set_bool(OBJECT(&s->soc), true, "realized", 322 &error_abort); 323 324 /* register RAM */ 325 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 326 machine->ram_size, &error_fatal); 327 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 328 main_mem); 329 330 /* create device tree */ 331 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 332 333 riscv_find_and_load_firmware(machine, BIOS_FILENAME, 334 memmap[SIFIVE_U_DRAM].base); 335 336 if (machine->kernel_filename) { 337 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); 338 339 if (machine->initrd_filename) { 340 hwaddr start; 341 hwaddr end = riscv_load_initrd(machine->initrd_filename, 342 machine->ram_size, kernel_entry, 343 &start); 344 qemu_fdt_setprop_cell(s->fdt, "/chosen", 345 "linux,initrd-start", start); 346 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 347 end); 348 } 349 } 350 351 /* reset vector */ 352 uint32_t reset_vec[8] = { 353 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 354 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 355 0xf1402573, /* csrr a0, mhartid */ 356 #if defined(TARGET_RISCV32) 357 0x0182a283, /* lw t0, 24(t0) */ 358 #elif defined(TARGET_RISCV64) 359 0x0182b283, /* ld t0, 24(t0) */ 360 #endif 361 0x00028067, /* jr t0 */ 362 0x00000000, 363 memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ 364 0x00000000, 365 /* dtb: */ 366 }; 367 368 /* copy in the reset vector in little_endian byte order */ 369 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 370 reset_vec[i] = cpu_to_le32(reset_vec[i]); 371 } 372 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 373 memmap[SIFIVE_U_MROM].base, &address_space_memory); 374 375 /* copy in the device tree */ 376 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 377 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 378 error_report("not enough space to store device-tree"); 379 exit(1); 380 } 381 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 382 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 383 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 384 &address_space_memory); 385 } 386 387 static void riscv_sifive_u_soc_init(Object *obj) 388 { 389 MachineState *ms = MACHINE(qdev_get_machine()); 390 SiFiveUSoCState *s = RISCV_U_SOC(obj); 391 392 object_initialize_child(obj, "e-cluster", &s->e_cluster, 393 sizeof(s->e_cluster), TYPE_CPU_CLUSTER, 394 &error_abort, NULL); 395 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 396 397 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", 398 &s->e_cpus, sizeof(s->e_cpus), 399 TYPE_RISCV_HART_ARRAY, &error_abort, 400 NULL); 401 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 402 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 403 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 404 405 object_initialize_child(obj, "u-cluster", &s->u_cluster, 406 sizeof(s->u_cluster), TYPE_CPU_CLUSTER, 407 &error_abort, NULL); 408 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 409 410 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", 411 &s->u_cpus, sizeof(s->u_cpus), 412 TYPE_RISCV_HART_ARRAY, &error_abort, 413 NULL); 414 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 415 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 416 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); 417 418 sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), 419 TYPE_SIFIVE_U_PRCI); 420 sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), 421 TYPE_SIFIVE_U_OTP); 422 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); 423 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), 424 TYPE_CADENCE_GEM); 425 } 426 427 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 428 { 429 MachineState *ms = MACHINE(qdev_get_machine()); 430 SiFiveUSoCState *s = RISCV_U_SOC(dev); 431 const struct MemmapEntry *memmap = sifive_u_memmap; 432 MemoryRegion *system_memory = get_system_memory(); 433 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 434 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; 435 char *plic_hart_config; 436 size_t plic_hart_config_len; 437 int i; 438 Error *err = NULL; 439 NICInfo *nd = &nd_table[0]; 440 441 object_property_set_bool(OBJECT(&s->e_cpus), true, "realized", 442 &error_abort); 443 object_property_set_bool(OBJECT(&s->u_cpus), true, "realized", 444 &error_abort); 445 /* 446 * The cluster must be realized after the RISC-V hart array container, 447 * as the container's CPU object is only created on realize, and the 448 * CPU must exist and have been parented into the cluster before the 449 * cluster is realized. 450 */ 451 object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", 452 &error_abort); 453 object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", 454 &error_abort); 455 456 /* boot rom */ 457 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", 458 memmap[SIFIVE_U_MROM].size, &error_fatal); 459 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 460 mask_rom); 461 462 /* create PLIC hart topology configuration string */ 463 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 464 ms->smp.cpus; 465 plic_hart_config = g_malloc0(plic_hart_config_len); 466 for (i = 0; i < ms->smp.cpus; i++) { 467 if (i != 0) { 468 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 469 plic_hart_config_len); 470 } else { 471 strncat(plic_hart_config, "M", plic_hart_config_len); 472 } 473 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 474 } 475 476 /* MMIO */ 477 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 478 plic_hart_config, 479 SIFIVE_U_PLIC_NUM_SOURCES, 480 SIFIVE_U_PLIC_NUM_PRIORITIES, 481 SIFIVE_U_PLIC_PRIORITY_BASE, 482 SIFIVE_U_PLIC_PENDING_BASE, 483 SIFIVE_U_PLIC_ENABLE_BASE, 484 SIFIVE_U_PLIC_ENABLE_STRIDE, 485 SIFIVE_U_PLIC_CONTEXT_BASE, 486 SIFIVE_U_PLIC_CONTEXT_STRIDE, 487 memmap[SIFIVE_U_PLIC].size); 488 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 489 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 490 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 491 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 492 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 493 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 494 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 495 496 object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); 497 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); 498 499 object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); 500 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); 501 502 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { 503 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); 504 } 505 506 if (nd->used) { 507 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 508 qdev_set_nic_properties(DEVICE(&s->gem), nd); 509 } 510 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 511 &error_abort); 512 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); 513 if (err) { 514 error_propagate(errp, err); 515 return; 516 } 517 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 518 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 519 plic_gpios[SIFIVE_U_GEM_IRQ]); 520 521 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 522 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); 523 } 524 525 static void riscv_sifive_u_machine_init(MachineClass *mc) 526 { 527 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 528 mc->init = riscv_sifive_u_init; 529 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 530 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 531 mc->default_cpus = mc->min_cpus; 532 } 533 534 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) 535 536 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 537 { 538 DeviceClass *dc = DEVICE_CLASS(oc); 539 540 dc->realize = riscv_sifive_u_soc_realize; 541 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 542 dc->user_creatable = false; 543 } 544 545 static const TypeInfo riscv_sifive_u_soc_type_info = { 546 .name = TYPE_RISCV_U_SOC, 547 .parent = TYPE_DEVICE, 548 .instance_size = sizeof(SiFiveUSoCState), 549 .instance_init = riscv_sifive_u_soc_init, 550 .class_init = riscv_sifive_u_soc_class_init, 551 }; 552 553 static void riscv_sifive_u_soc_register_types(void) 554 { 555 type_register_static(&riscv_sifive_u_soc_type_info); 556 } 557 558 type_init(riscv_sifive_u_soc_register_types) 559