1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 18 * This board currently generates devicetree dynamically that indicates at least 19 * two harts and up to five harts. 20 * 21 * This program is free software; you can redistribute it and/or modify it 22 * under the terms and conditions of the GNU General Public License, 23 * version 2 or later, as published by the Free Software Foundation. 24 * 25 * This program is distributed in the hope it will be useful, but WITHOUT 26 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 27 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 28 * more details. 29 * 30 * You should have received a copy of the GNU General Public License along with 31 * this program. If not, see <http://www.gnu.org/licenses/>. 32 */ 33 34 #include "qemu/osdep.h" 35 #include "qemu/log.h" 36 #include "qemu/error-report.h" 37 #include "qapi/error.h" 38 #include "qapi/visitor.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/loader.h" 42 #include "hw/sysbus.h" 43 #include "hw/char/serial.h" 44 #include "hw/cpu/cluster.h" 45 #include "hw/misc/unimp.h" 46 #include "target/riscv/cpu.h" 47 #include "hw/riscv/riscv_hart.h" 48 #include "hw/riscv/sifive_plic.h" 49 #include "hw/riscv/sifive_clint.h" 50 #include "hw/riscv/sifive_uart.h" 51 #include "hw/riscv/sifive_u.h" 52 #include "hw/riscv/boot.h" 53 #include "chardev/char.h" 54 #include "net/eth.h" 55 #include "sysemu/arch_init.h" 56 #include "sysemu/device_tree.h" 57 #include "sysemu/runstate.h" 58 #include "sysemu/sysemu.h" 59 #include "exec/address-spaces.h" 60 61 #include <libfdt.h> 62 63 #if defined(TARGET_RISCV32) 64 # define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin" 65 #else 66 # define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" 67 #endif 68 69 static const struct MemmapEntry { 70 hwaddr base; 71 hwaddr size; 72 } sifive_u_memmap[] = { 73 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 74 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 75 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 76 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, 77 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 78 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, 79 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, 80 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, 81 [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 }, 82 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, 83 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, 84 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, 85 [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 }, 86 [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, 87 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 88 }; 89 90 #define OTP_SERIAL 1 91 #define GEM_REVISION 0x10070109 92 93 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 94 uint64_t mem_size, const char *cmdline) 95 { 96 MachineState *ms = MACHINE(qdev_get_machine()); 97 void *fdt; 98 int cpu; 99 uint32_t *cells; 100 char *nodename; 101 char ethclk_names[] = "pclk\0hclk"; 102 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 103 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 104 105 fdt = s->fdt = create_device_tree(&s->fdt_size); 106 if (!fdt) { 107 error_report("create_device_tree() failed"); 108 exit(1); 109 } 110 111 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 112 qemu_fdt_setprop_string(fdt, "/", "compatible", 113 "sifive,hifive-unleashed-a00"); 114 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 115 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 116 117 qemu_fdt_add_subnode(fdt, "/soc"); 118 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 119 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 120 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 121 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 122 123 hfclk_phandle = phandle++; 124 nodename = g_strdup_printf("/hfclk"); 125 qemu_fdt_add_subnode(fdt, nodename); 126 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 127 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 128 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 129 SIFIVE_U_HFCLK_FREQ); 130 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 131 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 132 g_free(nodename); 133 134 rtcclk_phandle = phandle++; 135 nodename = g_strdup_printf("/rtcclk"); 136 qemu_fdt_add_subnode(fdt, nodename); 137 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 138 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 139 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 140 SIFIVE_U_RTCCLK_FREQ); 141 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 142 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 143 g_free(nodename); 144 145 nodename = g_strdup_printf("/memory@%lx", 146 (long)memmap[SIFIVE_U_DRAM].base); 147 qemu_fdt_add_subnode(fdt, nodename); 148 qemu_fdt_setprop_cells(fdt, nodename, "reg", 149 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 150 mem_size >> 32, mem_size); 151 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 152 g_free(nodename); 153 154 qemu_fdt_add_subnode(fdt, "/cpus"); 155 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 156 SIFIVE_CLINT_TIMEBASE_FREQ); 157 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 158 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 159 160 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 161 int cpu_phandle = phandle++; 162 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 163 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 164 char *isa; 165 qemu_fdt_add_subnode(fdt, nodename); 166 /* cpu 0 is the management hart that does not have mmu */ 167 if (cpu != 0) { 168 #if defined(TARGET_RISCV32) 169 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 170 #else 171 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 172 #endif 173 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 174 } else { 175 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 176 } 177 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 178 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 179 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 180 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 181 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 182 qemu_fdt_add_subnode(fdt, intc); 183 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 184 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 185 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 186 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 187 g_free(isa); 188 g_free(intc); 189 g_free(nodename); 190 } 191 192 cells = g_new0(uint32_t, ms->smp.cpus * 4); 193 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 194 nodename = 195 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 196 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 197 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 198 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 199 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 200 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 201 g_free(nodename); 202 } 203 nodename = g_strdup_printf("/soc/clint@%lx", 204 (long)memmap[SIFIVE_U_CLINT].base); 205 qemu_fdt_add_subnode(fdt, nodename); 206 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 207 qemu_fdt_setprop_cells(fdt, nodename, "reg", 208 0x0, memmap[SIFIVE_U_CLINT].base, 209 0x0, memmap[SIFIVE_U_CLINT].size); 210 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 211 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 212 g_free(cells); 213 g_free(nodename); 214 215 nodename = g_strdup_printf("/soc/otp@%lx", 216 (long)memmap[SIFIVE_U_OTP].base); 217 qemu_fdt_add_subnode(fdt, nodename); 218 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 219 qemu_fdt_setprop_cells(fdt, nodename, "reg", 220 0x0, memmap[SIFIVE_U_OTP].base, 221 0x0, memmap[SIFIVE_U_OTP].size); 222 qemu_fdt_setprop_string(fdt, nodename, "compatible", 223 "sifive,fu540-c000-otp"); 224 g_free(nodename); 225 226 prci_phandle = phandle++; 227 nodename = g_strdup_printf("/soc/clock-controller@%lx", 228 (long)memmap[SIFIVE_U_PRCI].base); 229 qemu_fdt_add_subnode(fdt, nodename); 230 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 231 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 232 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 233 hfclk_phandle, rtcclk_phandle); 234 qemu_fdt_setprop_cells(fdt, nodename, "reg", 235 0x0, memmap[SIFIVE_U_PRCI].base, 236 0x0, memmap[SIFIVE_U_PRCI].size); 237 qemu_fdt_setprop_string(fdt, nodename, "compatible", 238 "sifive,fu540-c000-prci"); 239 g_free(nodename); 240 241 plic_phandle = phandle++; 242 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 243 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 244 nodename = 245 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 246 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 247 /* cpu 0 is the management hart that does not have S-mode */ 248 if (cpu == 0) { 249 cells[0] = cpu_to_be32(intc_phandle); 250 cells[1] = cpu_to_be32(IRQ_M_EXT); 251 } else { 252 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 253 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 254 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 255 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 256 } 257 g_free(nodename); 258 } 259 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 260 (long)memmap[SIFIVE_U_PLIC].base); 261 qemu_fdt_add_subnode(fdt, nodename); 262 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 263 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 264 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 265 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 266 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 267 qemu_fdt_setprop_cells(fdt, nodename, "reg", 268 0x0, memmap[SIFIVE_U_PLIC].base, 269 0x0, memmap[SIFIVE_U_PLIC].size); 270 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 271 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 272 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 273 g_free(cells); 274 g_free(nodename); 275 276 gpio_phandle = phandle++; 277 nodename = g_strdup_printf("/soc/gpio@%lx", 278 (long)memmap[SIFIVE_U_GPIO].base); 279 qemu_fdt_add_subnode(fdt, nodename); 280 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 281 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 282 prci_phandle, PRCI_CLK_TLCLK); 283 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 284 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 285 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 286 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 287 qemu_fdt_setprop_cells(fdt, nodename, "reg", 288 0x0, memmap[SIFIVE_U_GPIO].base, 289 0x0, memmap[SIFIVE_U_GPIO].size); 290 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 291 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 292 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 293 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 294 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 295 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 296 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 297 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 298 g_free(nodename); 299 300 nodename = g_strdup_printf("/gpio-restart"); 301 qemu_fdt_add_subnode(fdt, nodename); 302 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 303 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 304 g_free(nodename); 305 306 phy_phandle = phandle++; 307 nodename = g_strdup_printf("/soc/ethernet@%lx", 308 (long)memmap[SIFIVE_U_GEM].base); 309 qemu_fdt_add_subnode(fdt, nodename); 310 qemu_fdt_setprop_string(fdt, nodename, "compatible", 311 "sifive,fu540-c000-gem"); 312 qemu_fdt_setprop_cells(fdt, nodename, "reg", 313 0x0, memmap[SIFIVE_U_GEM].base, 314 0x0, memmap[SIFIVE_U_GEM].size, 315 0x0, memmap[SIFIVE_U_GEM_MGMT].base, 316 0x0, memmap[SIFIVE_U_GEM_MGMT].size); 317 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 318 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 319 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 320 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 321 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 322 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 323 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 324 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 325 sizeof(ethclk_names)); 326 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 327 s->soc.gem.conf.macaddr.a, ETH_ALEN); 328 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 329 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 330 331 qemu_fdt_add_subnode(fdt, "/aliases"); 332 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 333 334 g_free(nodename); 335 336 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 337 (long)memmap[SIFIVE_U_GEM].base); 338 qemu_fdt_add_subnode(fdt, nodename); 339 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 340 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 341 g_free(nodename); 342 343 nodename = g_strdup_printf("/soc/serial@%lx", 344 (long)memmap[SIFIVE_U_UART0].base); 345 qemu_fdt_add_subnode(fdt, nodename); 346 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 347 qemu_fdt_setprop_cells(fdt, nodename, "reg", 348 0x0, memmap[SIFIVE_U_UART0].base, 349 0x0, memmap[SIFIVE_U_UART0].size); 350 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 351 prci_phandle, PRCI_CLK_TLCLK); 352 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 353 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 354 355 qemu_fdt_add_subnode(fdt, "/chosen"); 356 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 357 if (cmdline) { 358 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 359 } 360 361 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 362 363 g_free(nodename); 364 } 365 366 static void sifive_u_machine_reset(void *opaque, int n, int level) 367 { 368 /* gpio pin active low triggers reset */ 369 if (!level) { 370 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 371 } 372 } 373 374 static void sifive_u_machine_init(MachineState *machine) 375 { 376 const struct MemmapEntry *memmap = sifive_u_memmap; 377 SiFiveUState *s = RISCV_U_MACHINE(machine); 378 MemoryRegion *system_memory = get_system_memory(); 379 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 380 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 381 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base; 382 int i; 383 384 /* Initialize SoC */ 385 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 386 object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", 387 &error_abort); 388 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 389 390 /* register RAM */ 391 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 392 machine->ram_size, &error_fatal); 393 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 394 main_mem); 395 396 /* register QSPI0 Flash */ 397 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 398 memmap[SIFIVE_U_FLASH0].size, &error_fatal); 399 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base, 400 flash0); 401 402 /* register gpio-restart */ 403 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 404 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 405 406 /* create device tree */ 407 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 408 409 if (s->start_in_flash) { 410 /* 411 * If start_in_flash property is given, assign s->msel to a value 412 * that representing booting from QSPI0 memory-mapped flash. 413 * 414 * This also means that when both start_in_flash and msel properties 415 * are given, start_in_flash takes the precedence over msel. 416 * 417 * Note this is to keep backward compatibility not to break existing 418 * users that use start_in_flash property. 419 */ 420 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 421 } 422 423 switch (s->msel) { 424 case MSEL_MEMMAP_QSPI0_FLASH: 425 start_addr = memmap[SIFIVE_U_FLASH0].base; 426 break; 427 case MSEL_L2LIM_QSPI0_FLASH: 428 case MSEL_L2LIM_QSPI2_SD: 429 start_addr = memmap[SIFIVE_U_L2LIM].base; 430 break; 431 default: 432 start_addr = memmap[SIFIVE_U_DRAM].base; 433 break; 434 } 435 436 riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL); 437 438 if (machine->kernel_filename) { 439 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, 440 NULL); 441 442 if (machine->initrd_filename) { 443 hwaddr start; 444 hwaddr end = riscv_load_initrd(machine->initrd_filename, 445 machine->ram_size, kernel_entry, 446 &start); 447 qemu_fdt_setprop_cell(s->fdt, "/chosen", 448 "linux,initrd-start", start); 449 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 450 end); 451 } 452 } 453 454 /* reset vector */ 455 uint32_t reset_vec[8] = { 456 s->msel, /* MSEL pin state */ 457 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 458 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */ 459 0xf1402573, /* csrr a0, mhartid */ 460 #if defined(TARGET_RISCV32) 461 0x0182a283, /* lw t0, 24(t0) */ 462 #elif defined(TARGET_RISCV64) 463 0x0182e283, /* lwu t0, 24(t0) */ 464 #endif 465 0x00028067, /* jr t0 */ 466 0x00000000, 467 start_addr, /* start: .dword */ 468 /* dtb: */ 469 }; 470 471 /* copy in the reset vector in little_endian byte order */ 472 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 473 reset_vec[i] = cpu_to_le32(reset_vec[i]); 474 } 475 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 476 memmap[SIFIVE_U_MROM].base, &address_space_memory); 477 478 /* copy in the device tree */ 479 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 480 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 481 error_report("not enough space to store device-tree"); 482 exit(1); 483 } 484 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 485 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 486 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 487 &address_space_memory); 488 } 489 490 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 491 { 492 SiFiveUState *s = RISCV_U_MACHINE(obj); 493 494 return s->start_in_flash; 495 } 496 497 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 498 { 499 SiFiveUState *s = RISCV_U_MACHINE(obj); 500 501 s->start_in_flash = value; 502 } 503 504 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 505 const char *name, void *opaque, 506 Error **errp) 507 { 508 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 509 } 510 511 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 512 const char *name, void *opaque, 513 Error **errp) 514 { 515 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 516 } 517 518 static void sifive_u_machine_instance_init(Object *obj) 519 { 520 SiFiveUState *s = RISCV_U_MACHINE(obj); 521 522 s->start_in_flash = false; 523 object_property_add_bool(obj, "start-in-flash", 524 sifive_u_machine_get_start_in_flash, 525 sifive_u_machine_set_start_in_flash); 526 object_property_set_description(obj, "start-in-flash", 527 "Set on to tell QEMU's ROM to jump to " 528 "flash. Otherwise QEMU will jump to DRAM " 529 "or L2LIM depending on the msel value"); 530 531 s->msel = 0; 532 object_property_add(obj, "msel", "uint32", 533 sifive_u_machine_get_uint32_prop, 534 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 535 object_property_set_description(obj, "msel", 536 "Mode Select (MSEL[3:0]) pin state"); 537 538 s->serial = OTP_SERIAL; 539 object_property_add(obj, "serial", "uint32", 540 sifive_u_machine_get_uint32_prop, 541 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 542 object_property_set_description(obj, "serial", "Board serial number"); 543 } 544 545 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 546 { 547 MachineClass *mc = MACHINE_CLASS(oc); 548 549 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 550 mc->init = sifive_u_machine_init; 551 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 552 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 553 mc->default_cpus = mc->min_cpus; 554 } 555 556 static const TypeInfo sifive_u_machine_typeinfo = { 557 .name = MACHINE_TYPE_NAME("sifive_u"), 558 .parent = TYPE_MACHINE, 559 .class_init = sifive_u_machine_class_init, 560 .instance_init = sifive_u_machine_instance_init, 561 .instance_size = sizeof(SiFiveUState), 562 }; 563 564 static void sifive_u_machine_init_register_types(void) 565 { 566 type_register_static(&sifive_u_machine_typeinfo); 567 } 568 569 type_init(sifive_u_machine_init_register_types) 570 571 static void sifive_u_soc_instance_init(Object *obj) 572 { 573 MachineState *ms = MACHINE(qdev_get_machine()); 574 SiFiveUSoCState *s = RISCV_U_SOC(obj); 575 576 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 577 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 578 579 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 580 TYPE_RISCV_HART_ARRAY); 581 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 582 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 583 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 584 585 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 586 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 587 588 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 589 TYPE_RISCV_HART_ARRAY); 590 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 591 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 592 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); 593 594 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 595 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 596 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 597 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 598 } 599 600 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 601 { 602 MachineState *ms = MACHINE(qdev_get_machine()); 603 SiFiveUSoCState *s = RISCV_U_SOC(dev); 604 const struct MemmapEntry *memmap = sifive_u_memmap; 605 MemoryRegion *system_memory = get_system_memory(); 606 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 607 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 608 char *plic_hart_config; 609 size_t plic_hart_config_len; 610 int i; 611 Error *err = NULL; 612 NICInfo *nd = &nd_table[0]; 613 614 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 615 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 616 /* 617 * The cluster must be realized after the RISC-V hart array container, 618 * as the container's CPU object is only created on realize, and the 619 * CPU must exist and have been parented into the cluster before the 620 * cluster is realized. 621 */ 622 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 623 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 624 625 /* boot rom */ 626 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 627 memmap[SIFIVE_U_MROM].size, &error_fatal); 628 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 629 mask_rom); 630 631 /* 632 * Add L2-LIM at reset size. 633 * This should be reduced in size as the L2 Cache Controller WayEnable 634 * register is incremented. Unfortunately I don't see a nice (or any) way 635 * to handle reducing or blocking out the L2 LIM while still allowing it 636 * be re returned to all enabled after a reset. For the time being, just 637 * leave it enabled all the time. This won't break anything, but will be 638 * too generous to misbehaving guests. 639 */ 640 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 641 memmap[SIFIVE_U_L2LIM].size, &error_fatal); 642 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, 643 l2lim_mem); 644 645 /* create PLIC hart topology configuration string */ 646 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 647 ms->smp.cpus; 648 plic_hart_config = g_malloc0(plic_hart_config_len); 649 for (i = 0; i < ms->smp.cpus; i++) { 650 if (i != 0) { 651 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 652 plic_hart_config_len); 653 } else { 654 strncat(plic_hart_config, "M", plic_hart_config_len); 655 } 656 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 657 } 658 659 /* MMIO */ 660 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 661 plic_hart_config, 662 SIFIVE_U_PLIC_NUM_SOURCES, 663 SIFIVE_U_PLIC_NUM_PRIORITIES, 664 SIFIVE_U_PLIC_PRIORITY_BASE, 665 SIFIVE_U_PLIC_PENDING_BASE, 666 SIFIVE_U_PLIC_ENABLE_BASE, 667 SIFIVE_U_PLIC_ENABLE_STRIDE, 668 SIFIVE_U_PLIC_CONTEXT_BASE, 669 SIFIVE_U_PLIC_CONTEXT_STRIDE, 670 memmap[SIFIVE_U_PLIC].size); 671 g_free(plic_hart_config); 672 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 673 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 674 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 675 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 676 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 677 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 678 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); 679 680 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 681 return; 682 } 683 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); 684 685 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 686 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 687 return; 688 } 689 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base); 690 691 /* Pass all GPIOs to the SOC layer so they are available to the board */ 692 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 693 694 /* Connect GPIO interrupts to the PLIC */ 695 for (i = 0; i < 16; i++) { 696 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 697 qdev_get_gpio_in(DEVICE(s->plic), 698 SIFIVE_U_GPIO_IRQ0 + i)); 699 } 700 701 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 702 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 703 return; 704 } 705 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); 706 707 if (nd->used) { 708 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 709 qdev_set_nic_properties(DEVICE(&s->gem), nd); 710 } 711 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 712 &error_abort); 713 sysbus_realize(SYS_BUS_DEVICE(&s->gem), &err); 714 if (err) { 715 error_propagate(errp, err); 716 return; 717 } 718 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 719 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 720 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 721 722 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 723 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); 724 725 create_unimplemented_device("riscv.sifive.u.dmc", 726 memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size); 727 } 728 729 static Property sifive_u_soc_props[] = { 730 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 731 DEFINE_PROP_END_OF_LIST() 732 }; 733 734 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 735 { 736 DeviceClass *dc = DEVICE_CLASS(oc); 737 738 device_class_set_props(dc, sifive_u_soc_props); 739 dc->realize = sifive_u_soc_realize; 740 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 741 dc->user_creatable = false; 742 } 743 744 static const TypeInfo sifive_u_soc_type_info = { 745 .name = TYPE_RISCV_U_SOC, 746 .parent = TYPE_DEVICE, 747 .instance_size = sizeof(SiFiveUSoCState), 748 .instance_init = sifive_u_soc_instance_init, 749 .class_init = sifive_u_soc_class_init, 750 }; 751 752 static void sifive_u_soc_register_types(void) 753 { 754 type_register_static(&sifive_u_soc_type_info); 755 } 756 757 type_init(sifive_u_soc_register_types) 758