1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 8) SPI0 connected to an SPI flash 19 * 9) SPI2 connected to an SD card 20 * 10) PWM0 and PWM1 21 * 22 * This board currently generates devicetree dynamically that indicates at least 23 * two harts and up to five harts. 24 * 25 * This program is free software; you can redistribute it and/or modify it 26 * under the terms and conditions of the GNU General Public License, 27 * version 2 or later, as published by the Free Software Foundation. 28 * 29 * This program is distributed in the hope it will be useful, but WITHOUT 30 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 31 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 32 * more details. 33 * 34 * You should have received a copy of the GNU General Public License along with 35 * this program. If not, see <http://www.gnu.org/licenses/>. 36 */ 37 38 #include "qemu/osdep.h" 39 #include "qemu/error-report.h" 40 #include "qapi/error.h" 41 #include "qapi/visitor.h" 42 #include "hw/boards.h" 43 #include "hw/irq.h" 44 #include "hw/loader.h" 45 #include "hw/sysbus.h" 46 #include "hw/char/serial.h" 47 #include "hw/cpu/cluster.h" 48 #include "hw/misc/unimp.h" 49 #include "hw/sd/sd.h" 50 #include "hw/ssi/ssi.h" 51 #include "target/riscv/cpu.h" 52 #include "hw/riscv/riscv_hart.h" 53 #include "hw/riscv/sifive_u.h" 54 #include "hw/riscv/boot.h" 55 #include "hw/char/sifive_uart.h" 56 #include "hw/intc/riscv_aclint.h" 57 #include "hw/intc/sifive_plic.h" 58 #include "chardev/char.h" 59 #include "net/eth.h" 60 #include "sysemu/device_tree.h" 61 #include "sysemu/runstate.h" 62 #include "sysemu/sysemu.h" 63 64 #include <libfdt.h> 65 66 /* CLINT timebase frequency */ 67 #define CLINT_TIMEBASE_FREQ 1000000 68 69 static const MemMapEntry sifive_u_memmap[] = { 70 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 71 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 72 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 73 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 74 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 75 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 76 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 77 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 78 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 79 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 80 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 }, 81 [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 }, 82 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, 83 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, 84 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 85 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 86 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 87 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 88 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 89 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 90 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 91 }; 92 93 #define OTP_SERIAL 1 94 #define GEM_REVISION 0x10070109 95 96 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, 97 bool is_32_bit) 98 { 99 MachineState *ms = MACHINE(s); 100 uint64_t mem_size = ms->ram_size; 101 void *fdt; 102 int cpu; 103 uint32_t *cells; 104 char *nodename; 105 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 106 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 107 static const char * const ethclk_names[2] = { "pclk", "hclk" }; 108 static const char * const clint_compat[2] = { 109 "sifive,clint0", "riscv,clint0" 110 }; 111 static const char * const plic_compat[2] = { 112 "sifive,plic-1.0.0", "riscv,plic0" 113 }; 114 115 fdt = ms->fdt = create_device_tree(&s->fdt_size); 116 if (!fdt) { 117 error_report("create_device_tree() failed"); 118 exit(1); 119 } 120 121 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 122 qemu_fdt_setprop_string(fdt, "/", "compatible", 123 "sifive,hifive-unleashed-a00"); 124 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 125 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 126 127 qemu_fdt_add_subnode(fdt, "/soc"); 128 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 129 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 130 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 131 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 132 133 hfclk_phandle = phandle++; 134 nodename = g_strdup_printf("/hfclk"); 135 qemu_fdt_add_subnode(fdt, nodename); 136 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 137 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 138 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 139 SIFIVE_U_HFCLK_FREQ); 140 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 141 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 142 g_free(nodename); 143 144 rtcclk_phandle = phandle++; 145 nodename = g_strdup_printf("/rtcclk"); 146 qemu_fdt_add_subnode(fdt, nodename); 147 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 148 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 149 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 150 SIFIVE_U_RTCCLK_FREQ); 151 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 152 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 153 g_free(nodename); 154 155 nodename = g_strdup_printf("/memory@%lx", 156 (long)memmap[SIFIVE_U_DEV_DRAM].base); 157 qemu_fdt_add_subnode(fdt, nodename); 158 qemu_fdt_setprop_cells(fdt, nodename, "reg", 159 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 160 mem_size >> 32, mem_size); 161 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 162 g_free(nodename); 163 164 qemu_fdt_add_subnode(fdt, "/cpus"); 165 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 166 CLINT_TIMEBASE_FREQ); 167 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 168 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 169 170 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 171 int cpu_phandle = phandle++; 172 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 173 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 174 char *isa; 175 qemu_fdt_add_subnode(fdt, nodename); 176 /* cpu 0 is the management hart that does not have mmu */ 177 if (cpu != 0) { 178 if (is_32_bit) { 179 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 180 } else { 181 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 182 } 183 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 184 } else { 185 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 186 } 187 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 188 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 189 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 190 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 191 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 192 qemu_fdt_add_subnode(fdt, intc); 193 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 194 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 195 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 196 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 197 g_free(isa); 198 g_free(intc); 199 g_free(nodename); 200 } 201 202 cells = g_new0(uint32_t, ms->smp.cpus * 4); 203 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 204 nodename = 205 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 206 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 207 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 208 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 209 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 210 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 211 g_free(nodename); 212 } 213 nodename = g_strdup_printf("/soc/clint@%lx", 214 (long)memmap[SIFIVE_U_DEV_CLINT].base); 215 qemu_fdt_add_subnode(fdt, nodename); 216 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 217 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 218 qemu_fdt_setprop_cells(fdt, nodename, "reg", 219 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 220 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 221 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 222 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 223 g_free(cells); 224 g_free(nodename); 225 226 nodename = g_strdup_printf("/soc/otp@%lx", 227 (long)memmap[SIFIVE_U_DEV_OTP].base); 228 qemu_fdt_add_subnode(fdt, nodename); 229 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 230 qemu_fdt_setprop_cells(fdt, nodename, "reg", 231 0x0, memmap[SIFIVE_U_DEV_OTP].base, 232 0x0, memmap[SIFIVE_U_DEV_OTP].size); 233 qemu_fdt_setprop_string(fdt, nodename, "compatible", 234 "sifive,fu540-c000-otp"); 235 g_free(nodename); 236 237 prci_phandle = phandle++; 238 nodename = g_strdup_printf("/soc/clock-controller@%lx", 239 (long)memmap[SIFIVE_U_DEV_PRCI].base); 240 qemu_fdt_add_subnode(fdt, nodename); 241 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 242 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 243 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 244 hfclk_phandle, rtcclk_phandle); 245 qemu_fdt_setprop_cells(fdt, nodename, "reg", 246 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 247 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 248 qemu_fdt_setprop_string(fdt, nodename, "compatible", 249 "sifive,fu540-c000-prci"); 250 g_free(nodename); 251 252 plic_phandle = phandle++; 253 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 254 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 255 nodename = 256 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 257 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 258 /* cpu 0 is the management hart that does not have S-mode */ 259 if (cpu == 0) { 260 cells[0] = cpu_to_be32(intc_phandle); 261 cells[1] = cpu_to_be32(IRQ_M_EXT); 262 } else { 263 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 264 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 265 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 266 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 267 } 268 g_free(nodename); 269 } 270 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 271 (long)memmap[SIFIVE_U_DEV_PLIC].base); 272 qemu_fdt_add_subnode(fdt, nodename); 273 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 274 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 275 (char **)&plic_compat, ARRAY_SIZE(plic_compat)); 276 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 277 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 278 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 279 qemu_fdt_setprop_cells(fdt, nodename, "reg", 280 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 281 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 282 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 283 SIFIVE_U_PLIC_NUM_SOURCES - 1); 284 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 285 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 286 g_free(cells); 287 g_free(nodename); 288 289 gpio_phandle = phandle++; 290 nodename = g_strdup_printf("/soc/gpio@%lx", 291 (long)memmap[SIFIVE_U_DEV_GPIO].base); 292 qemu_fdt_add_subnode(fdt, nodename); 293 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 294 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 295 prci_phandle, PRCI_CLK_TLCLK); 296 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 297 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 298 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 299 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 300 qemu_fdt_setprop_cells(fdt, nodename, "reg", 301 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 302 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 303 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 304 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 305 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 306 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 307 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 308 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 309 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 310 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 311 g_free(nodename); 312 313 nodename = g_strdup_printf("/gpio-restart"); 314 qemu_fdt_add_subnode(fdt, nodename); 315 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 316 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 317 g_free(nodename); 318 319 nodename = g_strdup_printf("/soc/dma@%lx", 320 (long)memmap[SIFIVE_U_DEV_PDMA].base); 321 qemu_fdt_add_subnode(fdt, nodename); 322 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 323 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 324 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 325 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 326 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 327 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 328 qemu_fdt_setprop_cells(fdt, nodename, "reg", 329 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 330 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 331 qemu_fdt_setprop_string(fdt, nodename, "compatible", 332 "sifive,fu540-c000-pdma"); 333 g_free(nodename); 334 335 nodename = g_strdup_printf("/soc/cache-controller@%lx", 336 (long)memmap[SIFIVE_U_DEV_L2CC].base); 337 qemu_fdt_add_subnode(fdt, nodename); 338 qemu_fdt_setprop_cells(fdt, nodename, "reg", 339 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 340 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 341 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 342 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 343 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 344 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 345 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 346 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 347 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 348 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 349 qemu_fdt_setprop_string(fdt, nodename, "compatible", 350 "sifive,fu540-c000-ccache"); 351 g_free(nodename); 352 353 nodename = g_strdup_printf("/soc/spi@%lx", 354 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 355 qemu_fdt_add_subnode(fdt, nodename); 356 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 357 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 358 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 359 prci_phandle, PRCI_CLK_TLCLK); 360 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); 361 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 362 qemu_fdt_setprop_cells(fdt, nodename, "reg", 363 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, 364 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); 365 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 366 g_free(nodename); 367 368 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", 369 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 370 qemu_fdt_add_subnode(fdt, nodename); 371 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); 372 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); 373 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); 374 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 375 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); 376 g_free(nodename); 377 378 nodename = g_strdup_printf("/soc/spi@%lx", 379 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 380 qemu_fdt_add_subnode(fdt, nodename); 381 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 382 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 383 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 384 prci_phandle, PRCI_CLK_TLCLK); 385 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); 386 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 387 qemu_fdt_setprop_cells(fdt, nodename, "reg", 388 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, 389 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); 390 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 391 g_free(nodename); 392 393 nodename = g_strdup_printf("/soc/spi@%lx/flash@0", 394 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 395 qemu_fdt_add_subnode(fdt, nodename); 396 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); 397 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); 398 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); 399 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); 400 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 401 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); 402 g_free(nodename); 403 404 phy_phandle = phandle++; 405 nodename = g_strdup_printf("/soc/ethernet@%lx", 406 (long)memmap[SIFIVE_U_DEV_GEM].base); 407 qemu_fdt_add_subnode(fdt, nodename); 408 qemu_fdt_setprop_string(fdt, nodename, "compatible", 409 "sifive,fu540-c000-gem"); 410 qemu_fdt_setprop_cells(fdt, nodename, "reg", 411 0x0, memmap[SIFIVE_U_DEV_GEM].base, 412 0x0, memmap[SIFIVE_U_DEV_GEM].size, 413 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 414 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 415 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 416 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 417 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 418 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 419 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 420 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 421 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 422 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", 423 (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); 424 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 425 s->soc.gem.conf.macaddr.a, ETH_ALEN); 426 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 427 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 428 429 qemu_fdt_add_subnode(fdt, "/aliases"); 430 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 431 432 g_free(nodename); 433 434 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 435 (long)memmap[SIFIVE_U_DEV_GEM].base); 436 qemu_fdt_add_subnode(fdt, nodename); 437 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 438 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 439 g_free(nodename); 440 441 nodename = g_strdup_printf("/soc/pwm@%lx", 442 (long)memmap[SIFIVE_U_DEV_PWM0].base); 443 qemu_fdt_add_subnode(fdt, nodename); 444 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); 445 qemu_fdt_setprop_cells(fdt, nodename, "reg", 446 0x0, memmap[SIFIVE_U_DEV_PWM0].base, 447 0x0, memmap[SIFIVE_U_DEV_PWM0].size); 448 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 449 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 450 SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, 451 SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3); 452 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 453 prci_phandle, PRCI_CLK_TLCLK); 454 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); 455 g_free(nodename); 456 457 nodename = g_strdup_printf("/soc/pwm@%lx", 458 (long)memmap[SIFIVE_U_DEV_PWM1].base); 459 qemu_fdt_add_subnode(fdt, nodename); 460 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); 461 qemu_fdt_setprop_cells(fdt, nodename, "reg", 462 0x0, memmap[SIFIVE_U_DEV_PWM1].base, 463 0x0, memmap[SIFIVE_U_DEV_PWM1].size); 464 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 465 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 466 SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1, 467 SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3); 468 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 469 prci_phandle, PRCI_CLK_TLCLK); 470 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); 471 g_free(nodename); 472 473 nodename = g_strdup_printf("/soc/serial@%lx", 474 (long)memmap[SIFIVE_U_DEV_UART1].base); 475 qemu_fdt_add_subnode(fdt, nodename); 476 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 477 qemu_fdt_setprop_cells(fdt, nodename, "reg", 478 0x0, memmap[SIFIVE_U_DEV_UART1].base, 479 0x0, memmap[SIFIVE_U_DEV_UART1].size); 480 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 481 prci_phandle, PRCI_CLK_TLCLK); 482 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 483 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); 484 485 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); 486 g_free(nodename); 487 488 nodename = g_strdup_printf("/soc/serial@%lx", 489 (long)memmap[SIFIVE_U_DEV_UART0].base); 490 qemu_fdt_add_subnode(fdt, nodename); 491 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 492 qemu_fdt_setprop_cells(fdt, nodename, "reg", 493 0x0, memmap[SIFIVE_U_DEV_UART0].base, 494 0x0, memmap[SIFIVE_U_DEV_UART0].size); 495 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 496 prci_phandle, PRCI_CLK_TLCLK); 497 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 498 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 499 500 qemu_fdt_add_subnode(fdt, "/chosen"); 501 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 502 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 503 504 g_free(nodename); 505 } 506 507 static void sifive_u_machine_reset(void *opaque, int n, int level) 508 { 509 /* gpio pin active low triggers reset */ 510 if (!level) { 511 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 512 } 513 } 514 515 static void sifive_u_machine_init(MachineState *machine) 516 { 517 const MemMapEntry *memmap = sifive_u_memmap; 518 SiFiveUState *s = RISCV_U_MACHINE(machine); 519 MemoryRegion *system_memory = get_system_memory(); 520 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 521 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 522 target_ulong firmware_end_addr, kernel_start_addr; 523 const char *firmware_name; 524 uint32_t start_addr_hi32 = 0x00000000; 525 int i; 526 uint32_t fdt_load_addr; 527 uint64_t kernel_entry; 528 DriveInfo *dinfo; 529 BlockBackend *blk; 530 DeviceState *flash_dev, *sd_dev, *card_dev; 531 qemu_irq flash_cs, sd_cs; 532 533 /* Initialize SoC */ 534 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 535 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 536 &error_abort); 537 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 538 &error_abort); 539 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 540 541 /* register RAM */ 542 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 543 machine->ram); 544 545 /* register QSPI0 Flash */ 546 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 547 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 548 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 549 flash0); 550 551 /* register gpio-restart */ 552 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 553 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 554 555 /* load/create device tree */ 556 if (machine->dtb) { 557 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); 558 if (!machine->fdt) { 559 error_report("load_device_tree() failed"); 560 exit(1); 561 } 562 } else { 563 create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); 564 } 565 566 if (s->start_in_flash) { 567 /* 568 * If start_in_flash property is given, assign s->msel to a value 569 * that representing booting from QSPI0 memory-mapped flash. 570 * 571 * This also means that when both start_in_flash and msel properties 572 * are given, start_in_flash takes the precedence over msel. 573 * 574 * Note this is to keep backward compatibility not to break existing 575 * users that use start_in_flash property. 576 */ 577 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 578 } 579 580 switch (s->msel) { 581 case MSEL_MEMMAP_QSPI0_FLASH: 582 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 583 break; 584 case MSEL_L2LIM_QSPI0_FLASH: 585 case MSEL_L2LIM_QSPI2_SD: 586 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 587 break; 588 default: 589 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 590 break; 591 } 592 593 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); 594 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 595 start_addr, NULL); 596 597 if (machine->kernel_filename) { 598 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 599 firmware_end_addr); 600 601 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, 602 kernel_start_addr, true, NULL); 603 } else { 604 /* 605 * If dynamic firmware is used, it doesn't know where is the next mode 606 * if kernel argument is not set. 607 */ 608 kernel_entry = 0; 609 } 610 611 fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, 612 memmap[SIFIVE_U_DEV_DRAM].size, 613 machine); 614 riscv_load_fdt(fdt_load_addr, machine->fdt); 615 616 if (!riscv_is_32bit(&s->soc.u_cpus)) { 617 start_addr_hi32 = (uint64_t)start_addr >> 32; 618 } 619 620 /* reset vector */ 621 uint32_t reset_vec[12] = { 622 s->msel, /* MSEL pin state */ 623 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 624 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ 625 0xf1402573, /* csrr a0, mhartid */ 626 0, 627 0, 628 0x00028067, /* jr t0 */ 629 start_addr, /* start: .dword */ 630 start_addr_hi32, 631 fdt_load_addr, /* fdt_laddr: .dword */ 632 0x00000000, 633 0x00000000, 634 /* fw_dyn: */ 635 }; 636 if (riscv_is_32bit(&s->soc.u_cpus)) { 637 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ 638 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ 639 } else { 640 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ 641 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ 642 } 643 644 645 /* copy in the reset vector in little_endian byte order */ 646 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 647 reset_vec[i] = cpu_to_le32(reset_vec[i]); 648 } 649 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 650 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 651 652 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, 653 memmap[SIFIVE_U_DEV_MROM].size, 654 sizeof(reset_vec), kernel_entry); 655 656 /* Connect an SPI flash to SPI0 */ 657 flash_dev = qdev_new("is25wp256"); 658 dinfo = drive_get(IF_MTD, 0, 0); 659 if (dinfo) { 660 qdev_prop_set_drive_err(flash_dev, "drive", 661 blk_by_legacy_dinfo(dinfo), 662 &error_fatal); 663 } 664 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); 665 666 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 667 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); 668 669 /* Connect an SD card to SPI2 */ 670 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); 671 672 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); 673 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); 674 675 dinfo = drive_get(IF_SD, 0, 0); 676 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 677 card_dev = qdev_new(TYPE_SD_CARD_SPI); 678 qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); 679 qdev_realize_and_unref(card_dev, 680 qdev_get_child_bus(sd_dev, "sd-bus"), 681 &error_fatal); 682 } 683 684 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 685 { 686 SiFiveUState *s = RISCV_U_MACHINE(obj); 687 688 return s->start_in_flash; 689 } 690 691 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 692 { 693 SiFiveUState *s = RISCV_U_MACHINE(obj); 694 695 s->start_in_flash = value; 696 } 697 698 static void sifive_u_machine_instance_init(Object *obj) 699 { 700 SiFiveUState *s = RISCV_U_MACHINE(obj); 701 702 s->start_in_flash = false; 703 s->msel = 0; 704 object_property_add_uint32_ptr(obj, "msel", &s->msel, 705 OBJ_PROP_FLAG_READWRITE); 706 object_property_set_description(obj, "msel", 707 "Mode Select (MSEL[3:0]) pin state"); 708 709 s->serial = OTP_SERIAL; 710 object_property_add_uint32_ptr(obj, "serial", &s->serial, 711 OBJ_PROP_FLAG_READWRITE); 712 object_property_set_description(obj, "serial", "Board serial number"); 713 } 714 715 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 716 { 717 MachineClass *mc = MACHINE_CLASS(oc); 718 719 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 720 mc->init = sifive_u_machine_init; 721 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 722 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 723 mc->default_cpu_type = SIFIVE_U_CPU; 724 mc->default_cpus = mc->min_cpus; 725 mc->default_ram_id = "riscv.sifive.u.ram"; 726 727 object_class_property_add_bool(oc, "start-in-flash", 728 sifive_u_machine_get_start_in_flash, 729 sifive_u_machine_set_start_in_flash); 730 object_class_property_set_description(oc, "start-in-flash", 731 "Set on to tell QEMU's ROM to jump to " 732 "flash. Otherwise QEMU will jump to DRAM " 733 "or L2LIM depending on the msel value"); 734 } 735 736 static const TypeInfo sifive_u_machine_typeinfo = { 737 .name = MACHINE_TYPE_NAME("sifive_u"), 738 .parent = TYPE_MACHINE, 739 .class_init = sifive_u_machine_class_init, 740 .instance_init = sifive_u_machine_instance_init, 741 .instance_size = sizeof(SiFiveUState), 742 }; 743 744 static void sifive_u_machine_init_register_types(void) 745 { 746 type_register_static(&sifive_u_machine_typeinfo); 747 } 748 749 type_init(sifive_u_machine_init_register_types) 750 751 static void sifive_u_soc_instance_init(Object *obj) 752 { 753 SiFiveUSoCState *s = RISCV_U_SOC(obj); 754 755 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 756 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 757 758 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 759 TYPE_RISCV_HART_ARRAY); 760 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 761 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 762 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 763 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 764 765 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 766 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 767 768 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 769 TYPE_RISCV_HART_ARRAY); 770 771 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 772 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 773 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 774 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 775 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 776 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); 777 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); 778 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); 779 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); 780 } 781 782 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 783 { 784 MachineState *ms = MACHINE(qdev_get_machine()); 785 SiFiveUSoCState *s = RISCV_U_SOC(dev); 786 const MemMapEntry *memmap = sifive_u_memmap; 787 MemoryRegion *system_memory = get_system_memory(); 788 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 789 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 790 char *plic_hart_config; 791 int i, j; 792 793 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 794 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 795 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 796 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 797 798 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); 799 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); 800 /* 801 * The cluster must be realized after the RISC-V hart array container, 802 * as the container's CPU object is only created on realize, and the 803 * CPU must exist and have been parented into the cluster before the 804 * cluster is realized. 805 */ 806 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 807 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 808 809 /* boot rom */ 810 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 811 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 812 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 813 mask_rom); 814 815 /* 816 * Add L2-LIM at reset size. 817 * This should be reduced in size as the L2 Cache Controller WayEnable 818 * register is incremented. Unfortunately I don't see a nice (or any) way 819 * to handle reducing or blocking out the L2 LIM while still allowing it 820 * be re returned to all enabled after a reset. For the time being, just 821 * leave it enabled all the time. This won't break anything, but will be 822 * too generous to misbehaving guests. 823 */ 824 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 825 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 826 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 827 l2lim_mem); 828 829 /* create PLIC hart topology configuration string */ 830 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); 831 832 /* MMIO */ 833 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 834 plic_hart_config, ms->smp.cpus, 0, 835 SIFIVE_U_PLIC_NUM_SOURCES, 836 SIFIVE_U_PLIC_NUM_PRIORITIES, 837 SIFIVE_U_PLIC_PRIORITY_BASE, 838 SIFIVE_U_PLIC_PENDING_BASE, 839 SIFIVE_U_PLIC_ENABLE_BASE, 840 SIFIVE_U_PLIC_ENABLE_STRIDE, 841 SIFIVE_U_PLIC_CONTEXT_BASE, 842 SIFIVE_U_PLIC_CONTEXT_STRIDE, 843 memmap[SIFIVE_U_DEV_PLIC].size); 844 g_free(plic_hart_config); 845 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 846 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 847 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 848 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 849 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, 850 ms->smp.cpus, false); 851 riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + 852 RISCV_ACLINT_SWI_SIZE, 853 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 854 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 855 CLINT_TIMEBASE_FREQ, false); 856 857 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 858 return; 859 } 860 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 861 862 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 863 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 864 return; 865 } 866 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 867 868 /* Pass all GPIOs to the SOC layer so they are available to the board */ 869 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 870 871 /* Connect GPIO interrupts to the PLIC */ 872 for (i = 0; i < 16; i++) { 873 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 874 qdev_get_gpio_in(DEVICE(s->plic), 875 SIFIVE_U_GPIO_IRQ0 + i)); 876 } 877 878 /* PDMA */ 879 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 880 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 881 882 /* Connect PDMA interrupts to the PLIC */ 883 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 884 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 885 qdev_get_gpio_in(DEVICE(s->plic), 886 SIFIVE_U_PDMA_IRQ0 + i)); 887 } 888 889 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 890 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 891 return; 892 } 893 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 894 895 qemu_configure_nic_device(DEVICE(&s->gem), true, NULL); 896 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 897 &error_abort); 898 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 899 return; 900 } 901 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 902 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 903 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 904 905 /* PWM */ 906 for (i = 0; i < 2; i++) { 907 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { 908 return; 909 } 910 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, 911 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); 912 913 /* Connect PWM interrupts to the PLIC */ 914 for (j = 0; j < SIFIVE_PWM_IRQS; j++) { 915 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, 916 qdev_get_gpio_in(DEVICE(s->plic), 917 SIFIVE_U_PWM0_IRQ0 + (i * 4) + j)); 918 } 919 } 920 921 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 922 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 923 924 create_unimplemented_device("riscv.sifive.u.dmc", 925 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 926 927 create_unimplemented_device("riscv.sifive.u.l2cc", 928 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 929 930 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); 931 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, 932 memmap[SIFIVE_U_DEV_QSPI0].base); 933 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, 934 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); 935 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); 936 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, 937 memmap[SIFIVE_U_DEV_QSPI2].base); 938 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, 939 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); 940 } 941 942 static Property sifive_u_soc_props[] = { 943 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 944 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 945 DEFINE_PROP_END_OF_LIST() 946 }; 947 948 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 949 { 950 DeviceClass *dc = DEVICE_CLASS(oc); 951 952 device_class_set_props(dc, sifive_u_soc_props); 953 dc->realize = sifive_u_soc_realize; 954 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 955 dc->user_creatable = false; 956 } 957 958 static const TypeInfo sifive_u_soc_type_info = { 959 .name = TYPE_RISCV_U_SOC, 960 .parent = TYPE_DEVICE, 961 .instance_size = sizeof(SiFiveUSoCState), 962 .instance_init = sifive_u_soc_instance_init, 963 .class_init = sifive_u_soc_class_init, 964 }; 965 966 static void sifive_u_soc_register_types(void) 967 { 968 type_register_static(&sifive_u_soc_type_info); 969 } 970 971 type_init(sifive_u_soc_register_types) 972