1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 8) SPI0 connected to an SPI flash 19 * 9) SPI2 connected to an SD card 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/log.h" 39 #include "qemu/error-report.h" 40 #include "qapi/error.h" 41 #include "qapi/visitor.h" 42 #include "hw/boards.h" 43 #include "hw/irq.h" 44 #include "hw/loader.h" 45 #include "hw/sysbus.h" 46 #include "hw/char/serial.h" 47 #include "hw/cpu/cluster.h" 48 #include "hw/misc/unimp.h" 49 #include "hw/ssi/ssi.h" 50 #include "target/riscv/cpu.h" 51 #include "hw/riscv/riscv_hart.h" 52 #include "hw/riscv/sifive_u.h" 53 #include "hw/riscv/boot.h" 54 #include "hw/char/sifive_uart.h" 55 #include "hw/intc/sifive_clint.h" 56 #include "hw/intc/sifive_plic.h" 57 #include "chardev/char.h" 58 #include "net/eth.h" 59 #include "sysemu/arch_init.h" 60 #include "sysemu/device_tree.h" 61 #include "sysemu/runstate.h" 62 #include "sysemu/sysemu.h" 63 64 #include <libfdt.h> 65 66 static const MemMapEntry sifive_u_memmap[] = { 67 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 68 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 69 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 70 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 71 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 72 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 73 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 74 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 75 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 76 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 77 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, 78 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, 79 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 80 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 81 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 82 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 83 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 84 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 85 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 86 }; 87 88 #define OTP_SERIAL 1 89 #define GEM_REVISION 0x10070109 90 91 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, 92 uint64_t mem_size, const char *cmdline, bool is_32_bit) 93 { 94 MachineState *ms = MACHINE(qdev_get_machine()); 95 void *fdt; 96 int cpu; 97 uint32_t *cells; 98 char *nodename; 99 char ethclk_names[] = "pclk\0hclk"; 100 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 101 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 102 103 if (ms->dtb) { 104 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); 105 if (!fdt) { 106 error_report("load_device_tree() failed"); 107 exit(1); 108 } 109 goto update_bootargs; 110 } else { 111 fdt = s->fdt = create_device_tree(&s->fdt_size); 112 if (!fdt) { 113 error_report("create_device_tree() failed"); 114 exit(1); 115 } 116 } 117 118 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 119 qemu_fdt_setprop_string(fdt, "/", "compatible", 120 "sifive,hifive-unleashed-a00"); 121 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 122 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 123 124 qemu_fdt_add_subnode(fdt, "/soc"); 125 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 126 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 127 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 128 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 129 130 hfclk_phandle = phandle++; 131 nodename = g_strdup_printf("/hfclk"); 132 qemu_fdt_add_subnode(fdt, nodename); 133 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 134 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 135 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 136 SIFIVE_U_HFCLK_FREQ); 137 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 138 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 139 g_free(nodename); 140 141 rtcclk_phandle = phandle++; 142 nodename = g_strdup_printf("/rtcclk"); 143 qemu_fdt_add_subnode(fdt, nodename); 144 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 145 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 146 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 147 SIFIVE_U_RTCCLK_FREQ); 148 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 149 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 150 g_free(nodename); 151 152 nodename = g_strdup_printf("/memory@%lx", 153 (long)memmap[SIFIVE_U_DEV_DRAM].base); 154 qemu_fdt_add_subnode(fdt, nodename); 155 qemu_fdt_setprop_cells(fdt, nodename, "reg", 156 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 157 mem_size >> 32, mem_size); 158 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 159 g_free(nodename); 160 161 qemu_fdt_add_subnode(fdt, "/cpus"); 162 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 163 SIFIVE_CLINT_TIMEBASE_FREQ); 164 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 165 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 166 167 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 168 int cpu_phandle = phandle++; 169 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 170 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 171 char *isa; 172 qemu_fdt_add_subnode(fdt, nodename); 173 /* cpu 0 is the management hart that does not have mmu */ 174 if (cpu != 0) { 175 if (is_32_bit) { 176 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 177 } else { 178 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 179 } 180 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 181 } else { 182 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 183 } 184 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 185 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 186 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 187 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 188 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 189 qemu_fdt_add_subnode(fdt, intc); 190 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 191 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 192 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 193 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 194 g_free(isa); 195 g_free(intc); 196 g_free(nodename); 197 } 198 199 cells = g_new0(uint32_t, ms->smp.cpus * 4); 200 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 201 nodename = 202 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 203 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 204 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 205 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 206 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 207 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 208 g_free(nodename); 209 } 210 nodename = g_strdup_printf("/soc/clint@%lx", 211 (long)memmap[SIFIVE_U_DEV_CLINT].base); 212 qemu_fdt_add_subnode(fdt, nodename); 213 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 214 qemu_fdt_setprop_cells(fdt, nodename, "reg", 215 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 216 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 217 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 218 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 219 g_free(cells); 220 g_free(nodename); 221 222 nodename = g_strdup_printf("/soc/otp@%lx", 223 (long)memmap[SIFIVE_U_DEV_OTP].base); 224 qemu_fdt_add_subnode(fdt, nodename); 225 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 226 qemu_fdt_setprop_cells(fdt, nodename, "reg", 227 0x0, memmap[SIFIVE_U_DEV_OTP].base, 228 0x0, memmap[SIFIVE_U_DEV_OTP].size); 229 qemu_fdt_setprop_string(fdt, nodename, "compatible", 230 "sifive,fu540-c000-otp"); 231 g_free(nodename); 232 233 prci_phandle = phandle++; 234 nodename = g_strdup_printf("/soc/clock-controller@%lx", 235 (long)memmap[SIFIVE_U_DEV_PRCI].base); 236 qemu_fdt_add_subnode(fdt, nodename); 237 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 238 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 239 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 240 hfclk_phandle, rtcclk_phandle); 241 qemu_fdt_setprop_cells(fdt, nodename, "reg", 242 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 243 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 244 qemu_fdt_setprop_string(fdt, nodename, "compatible", 245 "sifive,fu540-c000-prci"); 246 g_free(nodename); 247 248 plic_phandle = phandle++; 249 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 250 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 251 nodename = 252 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 253 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 254 /* cpu 0 is the management hart that does not have S-mode */ 255 if (cpu == 0) { 256 cells[0] = cpu_to_be32(intc_phandle); 257 cells[1] = cpu_to_be32(IRQ_M_EXT); 258 } else { 259 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 260 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 261 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 262 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 263 } 264 g_free(nodename); 265 } 266 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 267 (long)memmap[SIFIVE_U_DEV_PLIC].base); 268 qemu_fdt_add_subnode(fdt, nodename); 269 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 270 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 271 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 272 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 273 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 274 qemu_fdt_setprop_cells(fdt, nodename, "reg", 275 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 276 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 277 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 278 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 279 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 280 g_free(cells); 281 g_free(nodename); 282 283 gpio_phandle = phandle++; 284 nodename = g_strdup_printf("/soc/gpio@%lx", 285 (long)memmap[SIFIVE_U_DEV_GPIO].base); 286 qemu_fdt_add_subnode(fdt, nodename); 287 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 288 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 289 prci_phandle, PRCI_CLK_TLCLK); 290 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 291 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 292 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 293 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 294 qemu_fdt_setprop_cells(fdt, nodename, "reg", 295 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 296 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 297 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 298 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 299 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 300 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 301 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 302 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 303 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 304 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 305 g_free(nodename); 306 307 nodename = g_strdup_printf("/gpio-restart"); 308 qemu_fdt_add_subnode(fdt, nodename); 309 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 310 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 311 g_free(nodename); 312 313 nodename = g_strdup_printf("/soc/dma@%lx", 314 (long)memmap[SIFIVE_U_DEV_PDMA].base); 315 qemu_fdt_add_subnode(fdt, nodename); 316 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 317 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 318 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 319 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 320 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 321 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 322 qemu_fdt_setprop_cells(fdt, nodename, "reg", 323 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 324 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 325 qemu_fdt_setprop_string(fdt, nodename, "compatible", 326 "sifive,fu540-c000-pdma"); 327 g_free(nodename); 328 329 nodename = g_strdup_printf("/soc/cache-controller@%lx", 330 (long)memmap[SIFIVE_U_DEV_L2CC].base); 331 qemu_fdt_add_subnode(fdt, nodename); 332 qemu_fdt_setprop_cells(fdt, nodename, "reg", 333 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 334 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 335 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 336 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 337 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 338 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 339 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 340 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 341 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 342 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 343 qemu_fdt_setprop_string(fdt, nodename, "compatible", 344 "sifive,fu540-c000-ccache"); 345 g_free(nodename); 346 347 nodename = g_strdup_printf("/soc/spi@%lx", 348 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 349 qemu_fdt_add_subnode(fdt, nodename); 350 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 351 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 352 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 353 prci_phandle, PRCI_CLK_TLCLK); 354 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); 355 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 356 qemu_fdt_setprop_cells(fdt, nodename, "reg", 357 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, 358 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); 359 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 360 g_free(nodename); 361 362 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", 363 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 364 qemu_fdt_add_subnode(fdt, nodename); 365 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); 366 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); 367 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); 368 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 369 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); 370 g_free(nodename); 371 372 nodename = g_strdup_printf("/soc/spi@%lx", 373 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 374 qemu_fdt_add_subnode(fdt, nodename); 375 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 376 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 377 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 378 prci_phandle, PRCI_CLK_TLCLK); 379 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); 380 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 381 qemu_fdt_setprop_cells(fdt, nodename, "reg", 382 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, 383 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); 384 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 385 g_free(nodename); 386 387 nodename = g_strdup_printf("/soc/spi@%lx/flash@0", 388 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 389 qemu_fdt_add_subnode(fdt, nodename); 390 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); 391 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); 392 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); 393 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); 394 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 395 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); 396 g_free(nodename); 397 398 phy_phandle = phandle++; 399 nodename = g_strdup_printf("/soc/ethernet@%lx", 400 (long)memmap[SIFIVE_U_DEV_GEM].base); 401 qemu_fdt_add_subnode(fdt, nodename); 402 qemu_fdt_setprop_string(fdt, nodename, "compatible", 403 "sifive,fu540-c000-gem"); 404 qemu_fdt_setprop_cells(fdt, nodename, "reg", 405 0x0, memmap[SIFIVE_U_DEV_GEM].base, 406 0x0, memmap[SIFIVE_U_DEV_GEM].size, 407 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 408 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 409 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 410 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 411 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 412 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 413 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 414 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 415 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 416 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 417 sizeof(ethclk_names)); 418 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 419 s->soc.gem.conf.macaddr.a, ETH_ALEN); 420 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 421 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 422 423 qemu_fdt_add_subnode(fdt, "/aliases"); 424 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 425 426 g_free(nodename); 427 428 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 429 (long)memmap[SIFIVE_U_DEV_GEM].base); 430 qemu_fdt_add_subnode(fdt, nodename); 431 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 432 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 433 g_free(nodename); 434 435 nodename = g_strdup_printf("/soc/serial@%lx", 436 (long)memmap[SIFIVE_U_DEV_UART1].base); 437 qemu_fdt_add_subnode(fdt, nodename); 438 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 439 qemu_fdt_setprop_cells(fdt, nodename, "reg", 440 0x0, memmap[SIFIVE_U_DEV_UART1].base, 441 0x0, memmap[SIFIVE_U_DEV_UART1].size); 442 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 443 prci_phandle, PRCI_CLK_TLCLK); 444 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 445 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); 446 447 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); 448 g_free(nodename); 449 450 nodename = g_strdup_printf("/soc/serial@%lx", 451 (long)memmap[SIFIVE_U_DEV_UART0].base); 452 qemu_fdt_add_subnode(fdt, nodename); 453 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 454 qemu_fdt_setprop_cells(fdt, nodename, "reg", 455 0x0, memmap[SIFIVE_U_DEV_UART0].base, 456 0x0, memmap[SIFIVE_U_DEV_UART0].size); 457 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 458 prci_phandle, PRCI_CLK_TLCLK); 459 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 460 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 461 462 qemu_fdt_add_subnode(fdt, "/chosen"); 463 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 464 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 465 466 g_free(nodename); 467 468 update_bootargs: 469 if (cmdline) { 470 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 471 } 472 } 473 474 static void sifive_u_machine_reset(void *opaque, int n, int level) 475 { 476 /* gpio pin active low triggers reset */ 477 if (!level) { 478 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 479 } 480 } 481 482 static void sifive_u_machine_init(MachineState *machine) 483 { 484 const MemMapEntry *memmap = sifive_u_memmap; 485 SiFiveUState *s = RISCV_U_MACHINE(machine); 486 MemoryRegion *system_memory = get_system_memory(); 487 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 488 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 489 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 490 target_ulong firmware_end_addr, kernel_start_addr; 491 uint32_t start_addr_hi32 = 0x00000000; 492 int i; 493 uint32_t fdt_load_addr; 494 uint64_t kernel_entry; 495 DriveInfo *dinfo; 496 DeviceState *flash_dev, *sd_dev; 497 qemu_irq flash_cs, sd_cs; 498 499 /* Initialize SoC */ 500 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 501 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 502 &error_abort); 503 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 504 &error_abort); 505 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 506 507 /* register RAM */ 508 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 509 machine->ram_size, &error_fatal); 510 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 511 main_mem); 512 513 /* register QSPI0 Flash */ 514 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 515 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 516 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 517 flash0); 518 519 /* register gpio-restart */ 520 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 521 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 522 523 /* create device tree */ 524 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 525 riscv_is_32bit(&s->soc.u_cpus)); 526 527 if (s->start_in_flash) { 528 /* 529 * If start_in_flash property is given, assign s->msel to a value 530 * that representing booting from QSPI0 memory-mapped flash. 531 * 532 * This also means that when both start_in_flash and msel properties 533 * are given, start_in_flash takes the precedence over msel. 534 * 535 * Note this is to keep backward compatibility not to break existing 536 * users that use start_in_flash property. 537 */ 538 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 539 } 540 541 switch (s->msel) { 542 case MSEL_MEMMAP_QSPI0_FLASH: 543 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 544 break; 545 case MSEL_L2LIM_QSPI0_FLASH: 546 case MSEL_L2LIM_QSPI2_SD: 547 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 548 break; 549 default: 550 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 551 break; 552 } 553 554 if (riscv_is_32bit(&s->soc.u_cpus)) { 555 firmware_end_addr = riscv_find_and_load_firmware(machine, 556 "opensbi-riscv32-generic-fw_dynamic.bin", 557 start_addr, NULL); 558 } else { 559 firmware_end_addr = riscv_find_and_load_firmware(machine, 560 "opensbi-riscv64-generic-fw_dynamic.bin", 561 start_addr, NULL); 562 } 563 564 if (machine->kernel_filename) { 565 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 566 firmware_end_addr); 567 568 kernel_entry = riscv_load_kernel(machine->kernel_filename, 569 kernel_start_addr, NULL); 570 571 if (machine->initrd_filename) { 572 hwaddr start; 573 hwaddr end = riscv_load_initrd(machine->initrd_filename, 574 machine->ram_size, kernel_entry, 575 &start); 576 qemu_fdt_setprop_cell(s->fdt, "/chosen", 577 "linux,initrd-start", start); 578 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 579 end); 580 } 581 } else { 582 /* 583 * If dynamic firmware is used, it doesn't know where is the next mode 584 * if kernel argument is not set. 585 */ 586 kernel_entry = 0; 587 } 588 589 /* Compute the fdt load address in dram */ 590 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, 591 machine->ram_size, s->fdt); 592 if (!riscv_is_32bit(&s->soc.u_cpus)) { 593 start_addr_hi32 = (uint64_t)start_addr >> 32; 594 } 595 596 /* reset vector */ 597 uint32_t reset_vec[11] = { 598 s->msel, /* MSEL pin state */ 599 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 600 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 601 0xf1402573, /* csrr a0, mhartid */ 602 0, 603 0, 604 0x00028067, /* jr t0 */ 605 start_addr, /* start: .dword */ 606 start_addr_hi32, 607 fdt_load_addr, /* fdt_laddr: .dword */ 608 0x00000000, 609 /* fw_dyn: */ 610 }; 611 if (riscv_is_32bit(&s->soc.u_cpus)) { 612 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ 613 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ 614 } else { 615 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ 616 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ 617 } 618 619 620 /* copy in the reset vector in little_endian byte order */ 621 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 622 reset_vec[i] = cpu_to_le32(reset_vec[i]); 623 } 624 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 625 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 626 627 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, 628 memmap[SIFIVE_U_DEV_MROM].size, 629 sizeof(reset_vec), kernel_entry); 630 631 /* Connect an SPI flash to SPI0 */ 632 flash_dev = qdev_new("is25wp256"); 633 dinfo = drive_get_next(IF_MTD); 634 if (dinfo) { 635 qdev_prop_set_drive_err(flash_dev, "drive", 636 blk_by_legacy_dinfo(dinfo), 637 &error_fatal); 638 } 639 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); 640 641 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 642 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); 643 644 /* Connect an SD card to SPI2 */ 645 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); 646 647 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); 648 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); 649 } 650 651 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 652 { 653 SiFiveUState *s = RISCV_U_MACHINE(obj); 654 655 return s->start_in_flash; 656 } 657 658 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 659 { 660 SiFiveUState *s = RISCV_U_MACHINE(obj); 661 662 s->start_in_flash = value; 663 } 664 665 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 666 const char *name, void *opaque, 667 Error **errp) 668 { 669 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 670 } 671 672 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 673 const char *name, void *opaque, 674 Error **errp) 675 { 676 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 677 } 678 679 static void sifive_u_machine_instance_init(Object *obj) 680 { 681 SiFiveUState *s = RISCV_U_MACHINE(obj); 682 683 s->start_in_flash = false; 684 s->msel = 0; 685 object_property_add(obj, "msel", "uint32", 686 sifive_u_machine_get_uint32_prop, 687 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 688 object_property_set_description(obj, "msel", 689 "Mode Select (MSEL[3:0]) pin state"); 690 691 s->serial = OTP_SERIAL; 692 object_property_add(obj, "serial", "uint32", 693 sifive_u_machine_get_uint32_prop, 694 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 695 object_property_set_description(obj, "serial", "Board serial number"); 696 } 697 698 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 699 { 700 MachineClass *mc = MACHINE_CLASS(oc); 701 702 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 703 mc->init = sifive_u_machine_init; 704 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 705 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 706 mc->default_cpu_type = SIFIVE_U_CPU; 707 mc->default_cpus = mc->min_cpus; 708 709 object_class_property_add_bool(oc, "start-in-flash", 710 sifive_u_machine_get_start_in_flash, 711 sifive_u_machine_set_start_in_flash); 712 object_class_property_set_description(oc, "start-in-flash", 713 "Set on to tell QEMU's ROM to jump to " 714 "flash. Otherwise QEMU will jump to DRAM " 715 "or L2LIM depending on the msel value"); 716 } 717 718 static const TypeInfo sifive_u_machine_typeinfo = { 719 .name = MACHINE_TYPE_NAME("sifive_u"), 720 .parent = TYPE_MACHINE, 721 .class_init = sifive_u_machine_class_init, 722 .instance_init = sifive_u_machine_instance_init, 723 .instance_size = sizeof(SiFiveUState), 724 }; 725 726 static void sifive_u_machine_init_register_types(void) 727 { 728 type_register_static(&sifive_u_machine_typeinfo); 729 } 730 731 type_init(sifive_u_machine_init_register_types) 732 733 static void sifive_u_soc_instance_init(Object *obj) 734 { 735 SiFiveUSoCState *s = RISCV_U_SOC(obj); 736 737 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 738 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 739 740 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 741 TYPE_RISCV_HART_ARRAY); 742 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 743 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 744 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 745 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 746 747 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 748 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 749 750 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 751 TYPE_RISCV_HART_ARRAY); 752 753 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 754 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 755 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 756 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 757 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 758 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); 759 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); 760 } 761 762 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 763 { 764 MachineState *ms = MACHINE(qdev_get_machine()); 765 SiFiveUSoCState *s = RISCV_U_SOC(dev); 766 const MemMapEntry *memmap = sifive_u_memmap; 767 MemoryRegion *system_memory = get_system_memory(); 768 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 769 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 770 char *plic_hart_config; 771 size_t plic_hart_config_len; 772 int i; 773 NICInfo *nd = &nd_table[0]; 774 775 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 776 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 777 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 778 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 779 780 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 781 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 782 /* 783 * The cluster must be realized after the RISC-V hart array container, 784 * as the container's CPU object is only created on realize, and the 785 * CPU must exist and have been parented into the cluster before the 786 * cluster is realized. 787 */ 788 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 789 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 790 791 /* boot rom */ 792 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 793 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 794 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 795 mask_rom); 796 797 /* 798 * Add L2-LIM at reset size. 799 * This should be reduced in size as the L2 Cache Controller WayEnable 800 * register is incremented. Unfortunately I don't see a nice (or any) way 801 * to handle reducing or blocking out the L2 LIM while still allowing it 802 * be re returned to all enabled after a reset. For the time being, just 803 * leave it enabled all the time. This won't break anything, but will be 804 * too generous to misbehaving guests. 805 */ 806 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 807 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 808 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 809 l2lim_mem); 810 811 /* create PLIC hart topology configuration string */ 812 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 813 ms->smp.cpus; 814 plic_hart_config = g_malloc0(plic_hart_config_len); 815 for (i = 0; i < ms->smp.cpus; i++) { 816 if (i != 0) { 817 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 818 plic_hart_config_len); 819 } else { 820 strncat(plic_hart_config, "M", plic_hart_config_len); 821 } 822 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 823 } 824 825 /* MMIO */ 826 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 827 plic_hart_config, 0, 828 SIFIVE_U_PLIC_NUM_SOURCES, 829 SIFIVE_U_PLIC_NUM_PRIORITIES, 830 SIFIVE_U_PLIC_PRIORITY_BASE, 831 SIFIVE_U_PLIC_PENDING_BASE, 832 SIFIVE_U_PLIC_ENABLE_BASE, 833 SIFIVE_U_PLIC_ENABLE_STRIDE, 834 SIFIVE_U_PLIC_CONTEXT_BASE, 835 SIFIVE_U_PLIC_CONTEXT_STRIDE, 836 memmap[SIFIVE_U_DEV_PLIC].size); 837 g_free(plic_hart_config); 838 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 839 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 840 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 841 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 842 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, 843 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, 844 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 845 SIFIVE_CLINT_TIMEBASE_FREQ, false); 846 847 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 848 return; 849 } 850 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 851 852 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 853 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 854 return; 855 } 856 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 857 858 /* Pass all GPIOs to the SOC layer so they are available to the board */ 859 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 860 861 /* Connect GPIO interrupts to the PLIC */ 862 for (i = 0; i < 16; i++) { 863 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 864 qdev_get_gpio_in(DEVICE(s->plic), 865 SIFIVE_U_GPIO_IRQ0 + i)); 866 } 867 868 /* PDMA */ 869 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 870 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 871 872 /* Connect PDMA interrupts to the PLIC */ 873 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 874 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 875 qdev_get_gpio_in(DEVICE(s->plic), 876 SIFIVE_U_PDMA_IRQ0 + i)); 877 } 878 879 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 880 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 881 return; 882 } 883 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 884 885 /* FIXME use qdev NIC properties instead of nd_table[] */ 886 if (nd->used) { 887 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 888 qdev_set_nic_properties(DEVICE(&s->gem), nd); 889 } 890 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 891 &error_abort); 892 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 893 return; 894 } 895 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 896 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 897 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 898 899 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 900 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 901 902 create_unimplemented_device("riscv.sifive.u.dmc", 903 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 904 905 create_unimplemented_device("riscv.sifive.u.l2cc", 906 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 907 908 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); 909 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, 910 memmap[SIFIVE_U_DEV_QSPI0].base); 911 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, 912 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); 913 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); 914 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, 915 memmap[SIFIVE_U_DEV_QSPI2].base); 916 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, 917 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); 918 } 919 920 static Property sifive_u_soc_props[] = { 921 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 922 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 923 DEFINE_PROP_END_OF_LIST() 924 }; 925 926 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 927 { 928 DeviceClass *dc = DEVICE_CLASS(oc); 929 930 device_class_set_props(dc, sifive_u_soc_props); 931 dc->realize = sifive_u_soc_realize; 932 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 933 dc->user_creatable = false; 934 } 935 936 static const TypeInfo sifive_u_soc_type_info = { 937 .name = TYPE_RISCV_U_SOC, 938 .parent = TYPE_DEVICE, 939 .instance_size = sizeof(SiFiveUSoCState), 940 .instance_init = sifive_u_soc_instance_init, 941 .class_init = sifive_u_soc_class_init, 942 }; 943 944 static void sifive_u_soc_register_types(void) 945 { 946 type_register_static(&sifive_u_soc_type_info); 947 } 948 949 type_init(sifive_u_soc_register_types) 950