1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * 7 * Provides a board compatible with the SiFive Freedom U SDK: 8 * 9 * 0) UART 10 * 1) CLINT (Core Level Interruptor) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This board currently uses a hardcoded devicetree that indicates one hart. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms and conditions of the GNU General Public License, 17 * version 2 or later, as published by the Free Software Foundation. 18 * 19 * This program is distributed in the hope it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 22 * more details. 23 * 24 * You should have received a copy of the GNU General Public License along with 25 * this program. If not, see <http://www.gnu.org/licenses/>. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "qapi/error.h" 32 #include "hw/hw.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/sysbus.h" 36 #include "hw/char/serial.h" 37 #include "target/riscv/cpu.h" 38 #include "hw/riscv/riscv_hart.h" 39 #include "hw/riscv/sifive_plic.h" 40 #include "hw/riscv/sifive_clint.h" 41 #include "hw/riscv/sifive_uart.h" 42 #include "hw/riscv/sifive_prci.h" 43 #include "hw/riscv/sifive_u.h" 44 #include "hw/riscv/boot.h" 45 #include "chardev/char.h" 46 #include "sysemu/arch_init.h" 47 #include "sysemu/device_tree.h" 48 #include "exec/address-spaces.h" 49 50 #include <libfdt.h> 51 52 static const struct MemmapEntry { 53 hwaddr base; 54 hwaddr size; 55 } sifive_u_memmap[] = { 56 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 57 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 58 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 59 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 60 [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, 61 [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, 62 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 63 [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, 64 }; 65 66 #define GEM_REVISION 0x10070109 67 68 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 69 uint64_t mem_size, const char *cmdline) 70 { 71 void *fdt; 72 int cpu; 73 uint32_t *cells; 74 char *nodename; 75 char ethclk_names[] = "pclk\0hclk\0tx_clk"; 76 uint32_t plic_phandle, ethclk_phandle, phandle = 1; 77 78 fdt = s->fdt = create_device_tree(&s->fdt_size); 79 if (!fdt) { 80 error_report("create_device_tree() failed"); 81 exit(1); 82 } 83 84 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 85 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 86 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 87 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 88 89 qemu_fdt_add_subnode(fdt, "/soc"); 90 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 91 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 92 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 93 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 94 95 nodename = g_strdup_printf("/memory@%lx", 96 (long)memmap[SIFIVE_U_DRAM].base); 97 qemu_fdt_add_subnode(fdt, nodename); 98 qemu_fdt_setprop_cells(fdt, nodename, "reg", 99 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 100 mem_size >> 32, mem_size); 101 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 102 g_free(nodename); 103 104 qemu_fdt_add_subnode(fdt, "/cpus"); 105 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 106 SIFIVE_CLINT_TIMEBASE_FREQ); 107 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 108 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 109 110 for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { 111 int cpu_phandle = phandle++; 112 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 113 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 114 char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); 115 qemu_fdt_add_subnode(fdt, nodename); 116 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 117 SIFIVE_U_CLOCK_FREQ); 118 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 119 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 120 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 121 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 122 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 123 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 124 qemu_fdt_add_subnode(fdt, intc); 125 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 126 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); 127 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 128 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 129 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 130 g_free(isa); 131 g_free(intc); 132 g_free(nodename); 133 } 134 135 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 136 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 137 nodename = 138 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 139 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 140 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 141 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 142 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 143 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 144 g_free(nodename); 145 } 146 nodename = g_strdup_printf("/soc/clint@%lx", 147 (long)memmap[SIFIVE_U_CLINT].base); 148 qemu_fdt_add_subnode(fdt, nodename); 149 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 150 qemu_fdt_setprop_cells(fdt, nodename, "reg", 151 0x0, memmap[SIFIVE_U_CLINT].base, 152 0x0, memmap[SIFIVE_U_CLINT].size); 153 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 154 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 155 g_free(cells); 156 g_free(nodename); 157 158 plic_phandle = phandle++; 159 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 160 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 161 nodename = 162 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 163 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 164 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 165 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 166 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 167 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 168 g_free(nodename); 169 } 170 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 171 (long)memmap[SIFIVE_U_PLIC].base); 172 qemu_fdt_add_subnode(fdt, nodename); 173 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 174 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 175 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 176 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 177 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 178 qemu_fdt_setprop_cells(fdt, nodename, "reg", 179 0x0, memmap[SIFIVE_U_PLIC].base, 180 0x0, memmap[SIFIVE_U_PLIC].size); 181 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 182 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); 183 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 184 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); 185 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); 186 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 187 g_free(cells); 188 g_free(nodename); 189 190 ethclk_phandle = phandle++; 191 nodename = g_strdup_printf("/soc/ethclk"); 192 qemu_fdt_add_subnode(fdt, nodename); 193 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 194 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 195 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 196 SIFIVE_U_GEM_CLOCK_FREQ); 197 qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); 198 qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle); 199 ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); 200 g_free(nodename); 201 202 nodename = g_strdup_printf("/soc/ethernet@%lx", 203 (long)memmap[SIFIVE_U_GEM].base); 204 qemu_fdt_add_subnode(fdt, nodename); 205 qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); 206 qemu_fdt_setprop_cells(fdt, nodename, "reg", 207 0x0, memmap[SIFIVE_U_GEM].base, 208 0x0, memmap[SIFIVE_U_GEM].size); 209 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 210 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 211 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 212 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 213 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 214 ethclk_phandle, ethclk_phandle, ethclk_phandle); 215 qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, 216 sizeof(ethclk_names)); 217 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); 218 qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); 219 g_free(nodename); 220 221 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 222 (long)memmap[SIFIVE_U_GEM].base); 223 qemu_fdt_add_subnode(fdt, nodename); 224 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); 225 g_free(nodename); 226 227 nodename = g_strdup_printf("/soc/uart@%lx", 228 (long)memmap[SIFIVE_U_UART0].base); 229 qemu_fdt_add_subnode(fdt, nodename); 230 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 231 qemu_fdt_setprop_cells(fdt, nodename, "reg", 232 0x0, memmap[SIFIVE_U_UART0].base, 233 0x0, memmap[SIFIVE_U_UART0].size); 234 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 235 SIFIVE_U_CLOCK_FREQ / 2); 236 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 237 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 238 239 qemu_fdt_add_subnode(fdt, "/chosen"); 240 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 241 if (cmdline) { 242 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 243 } 244 g_free(nodename); 245 } 246 247 static void riscv_sifive_u_init(MachineState *machine) 248 { 249 const struct MemmapEntry *memmap = sifive_u_memmap; 250 251 SiFiveUState *s = g_new0(SiFiveUState, 1); 252 MemoryRegion *system_memory = get_system_memory(); 253 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 254 int i; 255 256 /* Initialize SoC */ 257 object_initialize_child(OBJECT(machine), "soc", &s->soc, 258 sizeof(s->soc), TYPE_RISCV_U_SOC, 259 &error_abort, NULL); 260 object_property_set_bool(OBJECT(&s->soc), true, "realized", 261 &error_abort); 262 263 /* register RAM */ 264 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 265 machine->ram_size, &error_fatal); 266 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 267 main_mem); 268 269 /* create device tree */ 270 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 271 272 if (machine->firmware) { 273 riscv_load_firmware(machine->firmware, memmap[SIFIVE_U_DRAM].base); 274 } 275 276 if (machine->kernel_filename) { 277 riscv_load_kernel(machine->kernel_filename); 278 } 279 280 /* reset vector */ 281 uint32_t reset_vec[8] = { 282 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 283 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 284 0xf1402573, /* csrr a0, mhartid */ 285 #if defined(TARGET_RISCV32) 286 0x0182a283, /* lw t0, 24(t0) */ 287 #elif defined(TARGET_RISCV64) 288 0x0182b283, /* ld t0, 24(t0) */ 289 #endif 290 0x00028067, /* jr t0 */ 291 0x00000000, 292 memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ 293 0x00000000, 294 /* dtb: */ 295 }; 296 297 /* copy in the reset vector in little_endian byte order */ 298 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 299 reset_vec[i] = cpu_to_le32(reset_vec[i]); 300 } 301 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 302 memmap[SIFIVE_U_MROM].base, &address_space_memory); 303 304 /* copy in the device tree */ 305 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 306 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 307 error_report("not enough space to store device-tree"); 308 exit(1); 309 } 310 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 311 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 312 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 313 &address_space_memory); 314 } 315 316 static void riscv_sifive_u_soc_init(Object *obj) 317 { 318 SiFiveUSoCState *s = RISCV_U_SOC(obj); 319 320 object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), 321 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 322 object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", 323 &error_abort); 324 object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", 325 &error_abort); 326 327 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), 328 TYPE_CADENCE_GEM); 329 } 330 331 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 332 { 333 SiFiveUSoCState *s = RISCV_U_SOC(dev); 334 const struct MemmapEntry *memmap = sifive_u_memmap; 335 MemoryRegion *system_memory = get_system_memory(); 336 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 337 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; 338 char *plic_hart_config; 339 size_t plic_hart_config_len; 340 int i; 341 Error *err = NULL; 342 NICInfo *nd = &nd_table[0]; 343 344 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 345 &error_abort); 346 347 /* boot rom */ 348 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", 349 memmap[SIFIVE_U_MROM].size, &error_fatal); 350 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 351 mask_rom); 352 353 /* create PLIC hart topology configuration string */ 354 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus; 355 plic_hart_config = g_malloc0(plic_hart_config_len); 356 for (i = 0; i < smp_cpus; i++) { 357 if (i != 0) { 358 strncat(plic_hart_config, ",", plic_hart_config_len); 359 } 360 strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, 361 plic_hart_config_len); 362 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 363 } 364 365 /* MMIO */ 366 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 367 plic_hart_config, 368 SIFIVE_U_PLIC_NUM_SOURCES, 369 SIFIVE_U_PLIC_NUM_PRIORITIES, 370 SIFIVE_U_PLIC_PRIORITY_BASE, 371 SIFIVE_U_PLIC_PENDING_BASE, 372 SIFIVE_U_PLIC_ENABLE_BASE, 373 SIFIVE_U_PLIC_ENABLE_STRIDE, 374 SIFIVE_U_PLIC_CONTEXT_BASE, 375 SIFIVE_U_PLIC_CONTEXT_STRIDE, 376 memmap[SIFIVE_U_PLIC].size); 377 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 378 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 379 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 380 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 381 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 382 memmap[SIFIVE_U_CLINT].size, smp_cpus, 383 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 384 385 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { 386 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); 387 } 388 389 if (nd->used) { 390 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 391 qdev_set_nic_properties(DEVICE(&s->gem), nd); 392 } 393 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 394 &error_abort); 395 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); 396 if (err) { 397 error_propagate(errp, err); 398 return; 399 } 400 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 401 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 402 plic_gpios[SIFIVE_U_GEM_IRQ]); 403 } 404 405 static void riscv_sifive_u_machine_init(MachineClass *mc) 406 { 407 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 408 mc->init = riscv_sifive_u_init; 409 /* The real hardware has 5 CPUs, but one of them is a small embedded power 410 * management CPU. 411 */ 412 mc->max_cpus = 4; 413 } 414 415 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) 416 417 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 418 { 419 DeviceClass *dc = DEVICE_CLASS(oc); 420 421 dc->realize = riscv_sifive_u_soc_realize; 422 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 423 dc->user_creatable = false; 424 } 425 426 static const TypeInfo riscv_sifive_u_soc_type_info = { 427 .name = TYPE_RISCV_U_SOC, 428 .parent = TYPE_DEVICE, 429 .instance_size = sizeof(SiFiveUSoCState), 430 .instance_init = riscv_sifive_u_soc_init, 431 .class_init = riscv_sifive_u_soc_class_init, 432 }; 433 434 static void riscv_sifive_u_soc_register_types(void) 435 { 436 type_register_static(&riscv_sifive_u_soc_type_info); 437 } 438 439 type_init(riscv_sifive_u_soc_register_types) 440