1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 19 * This board currently generates devicetree dynamically that indicates at least 20 * two harts and up to five harts. 21 * 22 * This program is free software; you can redistribute it and/or modify it 23 * under the terms and conditions of the GNU General Public License, 24 * version 2 or later, as published by the Free Software Foundation. 25 * 26 * This program is distributed in the hope it will be useful, but WITHOUT 27 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 28 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 29 * more details. 30 * 31 * You should have received a copy of the GNU General Public License along with 32 * this program. If not, see <http://www.gnu.org/licenses/>. 33 */ 34 35 #include "qemu/osdep.h" 36 #include "qemu/log.h" 37 #include "qemu/error-report.h" 38 #include "qapi/error.h" 39 #include "qapi/visitor.h" 40 #include "hw/boards.h" 41 #include "hw/irq.h" 42 #include "hw/loader.h" 43 #include "hw/sysbus.h" 44 #include "hw/char/serial.h" 45 #include "hw/cpu/cluster.h" 46 #include "hw/misc/unimp.h" 47 #include "target/riscv/cpu.h" 48 #include "hw/riscv/riscv_hart.h" 49 #include "hw/riscv/sifive_u.h" 50 #include "hw/riscv/boot.h" 51 #include "hw/char/sifive_uart.h" 52 #include "hw/intc/sifive_clint.h" 53 #include "hw/intc/sifive_plic.h" 54 #include "chardev/char.h" 55 #include "net/eth.h" 56 #include "sysemu/arch_init.h" 57 #include "sysemu/device_tree.h" 58 #include "sysemu/runstate.h" 59 #include "sysemu/sysemu.h" 60 61 #include <libfdt.h> 62 63 static const struct MemmapEntry { 64 hwaddr base; 65 hwaddr size; 66 } sifive_u_memmap[] = { 67 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 68 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 69 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 70 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 71 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 72 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 73 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 74 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 75 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 76 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 77 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 78 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 79 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 80 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 81 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 82 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 83 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 84 }; 85 86 #define OTP_SERIAL 1 87 #define GEM_REVISION 0x10070109 88 89 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 90 uint64_t mem_size, const char *cmdline, bool is_32_bit) 91 { 92 MachineState *ms = MACHINE(qdev_get_machine()); 93 void *fdt; 94 int cpu; 95 uint32_t *cells; 96 char *nodename; 97 char ethclk_names[] = "pclk\0hclk"; 98 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 99 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 100 101 if (ms->dtb) { 102 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); 103 if (!fdt) { 104 error_report("load_device_tree() failed"); 105 exit(1); 106 } 107 goto update_bootargs; 108 } else { 109 fdt = s->fdt = create_device_tree(&s->fdt_size); 110 if (!fdt) { 111 error_report("create_device_tree() failed"); 112 exit(1); 113 } 114 } 115 116 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 117 qemu_fdt_setprop_string(fdt, "/", "compatible", 118 "sifive,hifive-unleashed-a00"); 119 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 120 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 121 122 qemu_fdt_add_subnode(fdt, "/soc"); 123 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 124 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 125 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 126 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 127 128 hfclk_phandle = phandle++; 129 nodename = g_strdup_printf("/hfclk"); 130 qemu_fdt_add_subnode(fdt, nodename); 131 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 132 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 133 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 134 SIFIVE_U_HFCLK_FREQ); 135 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 136 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 137 g_free(nodename); 138 139 rtcclk_phandle = phandle++; 140 nodename = g_strdup_printf("/rtcclk"); 141 qemu_fdt_add_subnode(fdt, nodename); 142 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 143 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 144 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 145 SIFIVE_U_RTCCLK_FREQ); 146 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 147 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 148 g_free(nodename); 149 150 nodename = g_strdup_printf("/memory@%lx", 151 (long)memmap[SIFIVE_U_DEV_DRAM].base); 152 qemu_fdt_add_subnode(fdt, nodename); 153 qemu_fdt_setprop_cells(fdt, nodename, "reg", 154 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 155 mem_size >> 32, mem_size); 156 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 157 g_free(nodename); 158 159 qemu_fdt_add_subnode(fdt, "/cpus"); 160 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 161 SIFIVE_CLINT_TIMEBASE_FREQ); 162 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 163 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 164 165 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 166 int cpu_phandle = phandle++; 167 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 168 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 169 char *isa; 170 qemu_fdt_add_subnode(fdt, nodename); 171 /* cpu 0 is the management hart that does not have mmu */ 172 if (cpu != 0) { 173 if (is_32_bit) { 174 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 175 } else { 176 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 177 } 178 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 179 } else { 180 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 181 } 182 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 183 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 184 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 185 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 186 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 187 qemu_fdt_add_subnode(fdt, intc); 188 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 189 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 190 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 191 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 192 g_free(isa); 193 g_free(intc); 194 g_free(nodename); 195 } 196 197 cells = g_new0(uint32_t, ms->smp.cpus * 4); 198 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 199 nodename = 200 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 201 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 202 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 203 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 204 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 205 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 206 g_free(nodename); 207 } 208 nodename = g_strdup_printf("/soc/clint@%lx", 209 (long)memmap[SIFIVE_U_DEV_CLINT].base); 210 qemu_fdt_add_subnode(fdt, nodename); 211 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 212 qemu_fdt_setprop_cells(fdt, nodename, "reg", 213 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 214 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 215 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 216 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 217 g_free(cells); 218 g_free(nodename); 219 220 nodename = g_strdup_printf("/soc/otp@%lx", 221 (long)memmap[SIFIVE_U_DEV_OTP].base); 222 qemu_fdt_add_subnode(fdt, nodename); 223 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 224 qemu_fdt_setprop_cells(fdt, nodename, "reg", 225 0x0, memmap[SIFIVE_U_DEV_OTP].base, 226 0x0, memmap[SIFIVE_U_DEV_OTP].size); 227 qemu_fdt_setprop_string(fdt, nodename, "compatible", 228 "sifive,fu540-c000-otp"); 229 g_free(nodename); 230 231 prci_phandle = phandle++; 232 nodename = g_strdup_printf("/soc/clock-controller@%lx", 233 (long)memmap[SIFIVE_U_DEV_PRCI].base); 234 qemu_fdt_add_subnode(fdt, nodename); 235 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 236 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 237 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 238 hfclk_phandle, rtcclk_phandle); 239 qemu_fdt_setprop_cells(fdt, nodename, "reg", 240 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 241 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 242 qemu_fdt_setprop_string(fdt, nodename, "compatible", 243 "sifive,fu540-c000-prci"); 244 g_free(nodename); 245 246 plic_phandle = phandle++; 247 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 248 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 249 nodename = 250 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 251 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 252 /* cpu 0 is the management hart that does not have S-mode */ 253 if (cpu == 0) { 254 cells[0] = cpu_to_be32(intc_phandle); 255 cells[1] = cpu_to_be32(IRQ_M_EXT); 256 } else { 257 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 258 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 259 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 260 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 261 } 262 g_free(nodename); 263 } 264 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 265 (long)memmap[SIFIVE_U_DEV_PLIC].base); 266 qemu_fdt_add_subnode(fdt, nodename); 267 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 268 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 269 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 270 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 271 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 272 qemu_fdt_setprop_cells(fdt, nodename, "reg", 273 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 274 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 275 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 276 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 277 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 278 g_free(cells); 279 g_free(nodename); 280 281 gpio_phandle = phandle++; 282 nodename = g_strdup_printf("/soc/gpio@%lx", 283 (long)memmap[SIFIVE_U_DEV_GPIO].base); 284 qemu_fdt_add_subnode(fdt, nodename); 285 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 286 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 287 prci_phandle, PRCI_CLK_TLCLK); 288 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 289 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 290 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 291 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 292 qemu_fdt_setprop_cells(fdt, nodename, "reg", 293 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 294 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 295 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 296 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 297 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 298 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 299 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 300 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 301 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 302 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 303 g_free(nodename); 304 305 nodename = g_strdup_printf("/gpio-restart"); 306 qemu_fdt_add_subnode(fdt, nodename); 307 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 308 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 309 g_free(nodename); 310 311 nodename = g_strdup_printf("/soc/dma@%lx", 312 (long)memmap[SIFIVE_U_DEV_PDMA].base); 313 qemu_fdt_add_subnode(fdt, nodename); 314 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 315 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 316 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 317 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 318 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 319 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 320 qemu_fdt_setprop_cells(fdt, nodename, "reg", 321 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 322 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 323 qemu_fdt_setprop_string(fdt, nodename, "compatible", 324 "sifive,fu540-c000-pdma"); 325 g_free(nodename); 326 327 nodename = g_strdup_printf("/soc/cache-controller@%lx", 328 (long)memmap[SIFIVE_U_DEV_L2CC].base); 329 qemu_fdt_add_subnode(fdt, nodename); 330 qemu_fdt_setprop_cells(fdt, nodename, "reg", 331 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 332 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 333 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 334 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 335 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 336 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 337 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 338 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 339 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 340 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 341 qemu_fdt_setprop_string(fdt, nodename, "compatible", 342 "sifive,fu540-c000-ccache"); 343 g_free(nodename); 344 345 phy_phandle = phandle++; 346 nodename = g_strdup_printf("/soc/ethernet@%lx", 347 (long)memmap[SIFIVE_U_DEV_GEM].base); 348 qemu_fdt_add_subnode(fdt, nodename); 349 qemu_fdt_setprop_string(fdt, nodename, "compatible", 350 "sifive,fu540-c000-gem"); 351 qemu_fdt_setprop_cells(fdt, nodename, "reg", 352 0x0, memmap[SIFIVE_U_DEV_GEM].base, 353 0x0, memmap[SIFIVE_U_DEV_GEM].size, 354 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 355 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 356 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 357 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 358 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 359 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 360 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 361 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 362 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 363 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 364 sizeof(ethclk_names)); 365 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 366 s->soc.gem.conf.macaddr.a, ETH_ALEN); 367 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 368 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 369 370 qemu_fdt_add_subnode(fdt, "/aliases"); 371 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 372 373 g_free(nodename); 374 375 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 376 (long)memmap[SIFIVE_U_DEV_GEM].base); 377 qemu_fdt_add_subnode(fdt, nodename); 378 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 379 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 380 g_free(nodename); 381 382 nodename = g_strdup_printf("/soc/serial@%lx", 383 (long)memmap[SIFIVE_U_DEV_UART1].base); 384 qemu_fdt_add_subnode(fdt, nodename); 385 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 386 qemu_fdt_setprop_cells(fdt, nodename, "reg", 387 0x0, memmap[SIFIVE_U_DEV_UART1].base, 388 0x0, memmap[SIFIVE_U_DEV_UART1].size); 389 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 390 prci_phandle, PRCI_CLK_TLCLK); 391 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 392 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); 393 394 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); 395 g_free(nodename); 396 397 nodename = g_strdup_printf("/soc/serial@%lx", 398 (long)memmap[SIFIVE_U_DEV_UART0].base); 399 qemu_fdt_add_subnode(fdt, nodename); 400 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 401 qemu_fdt_setprop_cells(fdt, nodename, "reg", 402 0x0, memmap[SIFIVE_U_DEV_UART0].base, 403 0x0, memmap[SIFIVE_U_DEV_UART0].size); 404 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 405 prci_phandle, PRCI_CLK_TLCLK); 406 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 407 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 408 409 qemu_fdt_add_subnode(fdt, "/chosen"); 410 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 411 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 412 413 g_free(nodename); 414 415 update_bootargs: 416 if (cmdline) { 417 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 418 } 419 } 420 421 static void sifive_u_machine_reset(void *opaque, int n, int level) 422 { 423 /* gpio pin active low triggers reset */ 424 if (!level) { 425 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 426 } 427 } 428 429 static void sifive_u_machine_init(MachineState *machine) 430 { 431 const struct MemmapEntry *memmap = sifive_u_memmap; 432 SiFiveUState *s = RISCV_U_MACHINE(machine); 433 MemoryRegion *system_memory = get_system_memory(); 434 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 435 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 436 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 437 target_ulong firmware_end_addr, kernel_start_addr; 438 uint32_t start_addr_hi32 = 0x00000000; 439 int i; 440 uint32_t fdt_load_addr; 441 uint64_t kernel_entry; 442 443 /* Initialize SoC */ 444 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 445 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 446 &error_abort); 447 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 448 &error_abort); 449 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 450 451 /* register RAM */ 452 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 453 machine->ram_size, &error_fatal); 454 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 455 main_mem); 456 457 /* register QSPI0 Flash */ 458 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 459 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 460 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 461 flash0); 462 463 /* register gpio-restart */ 464 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 465 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 466 467 /* create device tree */ 468 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 469 riscv_is_32bit(s->soc.u_cpus)); 470 471 if (s->start_in_flash) { 472 /* 473 * If start_in_flash property is given, assign s->msel to a value 474 * that representing booting from QSPI0 memory-mapped flash. 475 * 476 * This also means that when both start_in_flash and msel properties 477 * are given, start_in_flash takes the precedence over msel. 478 * 479 * Note this is to keep backward compatibility not to break existing 480 * users that use start_in_flash property. 481 */ 482 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 483 } 484 485 switch (s->msel) { 486 case MSEL_MEMMAP_QSPI0_FLASH: 487 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 488 break; 489 case MSEL_L2LIM_QSPI0_FLASH: 490 case MSEL_L2LIM_QSPI2_SD: 491 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 492 break; 493 default: 494 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 495 break; 496 } 497 498 if (riscv_is_32bit(s->soc.u_cpus)) { 499 firmware_end_addr = riscv_find_and_load_firmware(machine, 500 "opensbi-riscv32-generic-fw_dynamic.bin", 501 start_addr, NULL); 502 } else { 503 firmware_end_addr = riscv_find_and_load_firmware(machine, 504 "opensbi-riscv64-generic-fw_dynamic.bin", 505 start_addr, NULL); 506 } 507 508 if (machine->kernel_filename) { 509 kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus, 510 firmware_end_addr); 511 512 kernel_entry = riscv_load_kernel(machine->kernel_filename, 513 kernel_start_addr, NULL); 514 515 if (machine->initrd_filename) { 516 hwaddr start; 517 hwaddr end = riscv_load_initrd(machine->initrd_filename, 518 machine->ram_size, kernel_entry, 519 &start); 520 qemu_fdt_setprop_cell(s->fdt, "/chosen", 521 "linux,initrd-start", start); 522 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 523 end); 524 } 525 } else { 526 /* 527 * If dynamic firmware is used, it doesn't know where is the next mode 528 * if kernel argument is not set. 529 */ 530 kernel_entry = 0; 531 } 532 533 /* Compute the fdt load address in dram */ 534 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, 535 machine->ram_size, s->fdt); 536 if (!riscv_is_32bit(s->soc.u_cpus)) { 537 start_addr_hi32 = (uint64_t)start_addr >> 32; 538 } 539 540 /* reset vector */ 541 uint32_t reset_vec[11] = { 542 s->msel, /* MSEL pin state */ 543 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 544 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 545 0xf1402573, /* csrr a0, mhartid */ 546 0, 547 0, 548 0x00028067, /* jr t0 */ 549 start_addr, /* start: .dword */ 550 start_addr_hi32, 551 fdt_load_addr, /* fdt_laddr: .dword */ 552 0x00000000, 553 /* fw_dyn: */ 554 }; 555 if (riscv_is_32bit(s->soc.u_cpus)) { 556 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ 557 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ 558 } else { 559 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ 560 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ 561 } 562 563 564 /* copy in the reset vector in little_endian byte order */ 565 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 566 reset_vec[i] = cpu_to_le32(reset_vec[i]); 567 } 568 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 569 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 570 571 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, 572 memmap[SIFIVE_U_DEV_MROM].size, 573 sizeof(reset_vec), kernel_entry); 574 } 575 576 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 577 { 578 SiFiveUState *s = RISCV_U_MACHINE(obj); 579 580 return s->start_in_flash; 581 } 582 583 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 584 { 585 SiFiveUState *s = RISCV_U_MACHINE(obj); 586 587 s->start_in_flash = value; 588 } 589 590 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 591 const char *name, void *opaque, 592 Error **errp) 593 { 594 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 595 } 596 597 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 598 const char *name, void *opaque, 599 Error **errp) 600 { 601 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 602 } 603 604 static void sifive_u_machine_instance_init(Object *obj) 605 { 606 SiFiveUState *s = RISCV_U_MACHINE(obj); 607 608 s->start_in_flash = false; 609 s->msel = 0; 610 object_property_add(obj, "msel", "uint32", 611 sifive_u_machine_get_uint32_prop, 612 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 613 object_property_set_description(obj, "msel", 614 "Mode Select (MSEL[3:0]) pin state"); 615 616 s->serial = OTP_SERIAL; 617 object_property_add(obj, "serial", "uint32", 618 sifive_u_machine_get_uint32_prop, 619 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 620 object_property_set_description(obj, "serial", "Board serial number"); 621 } 622 623 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 624 { 625 MachineClass *mc = MACHINE_CLASS(oc); 626 627 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 628 mc->init = sifive_u_machine_init; 629 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 630 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 631 #if defined(TARGET_RISCV32) 632 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; 633 #elif defined(TARGET_RISCV64) 634 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; 635 #endif 636 mc->default_cpus = mc->min_cpus; 637 638 object_class_property_add_bool(oc, "start-in-flash", 639 sifive_u_machine_get_start_in_flash, 640 sifive_u_machine_set_start_in_flash); 641 object_class_property_set_description(oc, "start-in-flash", 642 "Set on to tell QEMU's ROM to jump to " 643 "flash. Otherwise QEMU will jump to DRAM " 644 "or L2LIM depending on the msel value"); 645 } 646 647 static const TypeInfo sifive_u_machine_typeinfo = { 648 .name = MACHINE_TYPE_NAME("sifive_u"), 649 .parent = TYPE_MACHINE, 650 .class_init = sifive_u_machine_class_init, 651 .instance_init = sifive_u_machine_instance_init, 652 .instance_size = sizeof(SiFiveUState), 653 }; 654 655 static void sifive_u_machine_init_register_types(void) 656 { 657 type_register_static(&sifive_u_machine_typeinfo); 658 } 659 660 type_init(sifive_u_machine_init_register_types) 661 662 static void sifive_u_soc_instance_init(Object *obj) 663 { 664 SiFiveUSoCState *s = RISCV_U_SOC(obj); 665 666 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 667 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 668 669 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 670 TYPE_RISCV_HART_ARRAY); 671 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 672 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 673 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 674 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 675 676 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 677 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 678 679 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 680 TYPE_RISCV_HART_ARRAY); 681 682 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 683 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 684 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 685 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 686 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 687 } 688 689 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 690 { 691 MachineState *ms = MACHINE(qdev_get_machine()); 692 SiFiveUSoCState *s = RISCV_U_SOC(dev); 693 const struct MemmapEntry *memmap = sifive_u_memmap; 694 MemoryRegion *system_memory = get_system_memory(); 695 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 696 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 697 char *plic_hart_config; 698 size_t plic_hart_config_len; 699 int i; 700 NICInfo *nd = &nd_table[0]; 701 702 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 703 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 704 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 705 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 706 707 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 708 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 709 /* 710 * The cluster must be realized after the RISC-V hart array container, 711 * as the container's CPU object is only created on realize, and the 712 * CPU must exist and have been parented into the cluster before the 713 * cluster is realized. 714 */ 715 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 716 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 717 718 /* boot rom */ 719 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 720 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 721 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 722 mask_rom); 723 724 /* 725 * Add L2-LIM at reset size. 726 * This should be reduced in size as the L2 Cache Controller WayEnable 727 * register is incremented. Unfortunately I don't see a nice (or any) way 728 * to handle reducing or blocking out the L2 LIM while still allowing it 729 * be re returned to all enabled after a reset. For the time being, just 730 * leave it enabled all the time. This won't break anything, but will be 731 * too generous to misbehaving guests. 732 */ 733 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 734 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 735 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 736 l2lim_mem); 737 738 /* create PLIC hart topology configuration string */ 739 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 740 ms->smp.cpus; 741 plic_hart_config = g_malloc0(plic_hart_config_len); 742 for (i = 0; i < ms->smp.cpus; i++) { 743 if (i != 0) { 744 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 745 plic_hart_config_len); 746 } else { 747 strncat(plic_hart_config, "M", plic_hart_config_len); 748 } 749 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 750 } 751 752 /* MMIO */ 753 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 754 plic_hart_config, 0, 755 SIFIVE_U_PLIC_NUM_SOURCES, 756 SIFIVE_U_PLIC_NUM_PRIORITIES, 757 SIFIVE_U_PLIC_PRIORITY_BASE, 758 SIFIVE_U_PLIC_PENDING_BASE, 759 SIFIVE_U_PLIC_ENABLE_BASE, 760 SIFIVE_U_PLIC_ENABLE_STRIDE, 761 SIFIVE_U_PLIC_CONTEXT_BASE, 762 SIFIVE_U_PLIC_CONTEXT_STRIDE, 763 memmap[SIFIVE_U_DEV_PLIC].size); 764 g_free(plic_hart_config); 765 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 766 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 767 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 768 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 769 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, 770 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, 771 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 772 SIFIVE_CLINT_TIMEBASE_FREQ, false); 773 774 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 775 return; 776 } 777 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 778 779 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 780 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 781 return; 782 } 783 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 784 785 /* Pass all GPIOs to the SOC layer so they are available to the board */ 786 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 787 788 /* Connect GPIO interrupts to the PLIC */ 789 for (i = 0; i < 16; i++) { 790 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 791 qdev_get_gpio_in(DEVICE(s->plic), 792 SIFIVE_U_GPIO_IRQ0 + i)); 793 } 794 795 /* PDMA */ 796 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 797 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 798 799 /* Connect PDMA interrupts to the PLIC */ 800 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 801 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 802 qdev_get_gpio_in(DEVICE(s->plic), 803 SIFIVE_U_PDMA_IRQ0 + i)); 804 } 805 806 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 807 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 808 return; 809 } 810 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 811 812 /* FIXME use qdev NIC properties instead of nd_table[] */ 813 if (nd->used) { 814 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 815 qdev_set_nic_properties(DEVICE(&s->gem), nd); 816 } 817 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 818 &error_abort); 819 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 820 return; 821 } 822 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 823 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 824 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 825 826 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 827 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 828 829 create_unimplemented_device("riscv.sifive.u.dmc", 830 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 831 832 create_unimplemented_device("riscv.sifive.u.l2cc", 833 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 834 } 835 836 static Property sifive_u_soc_props[] = { 837 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 838 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 839 DEFINE_PROP_END_OF_LIST() 840 }; 841 842 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 843 { 844 DeviceClass *dc = DEVICE_CLASS(oc); 845 846 device_class_set_props(dc, sifive_u_soc_props); 847 dc->realize = sifive_u_soc_realize; 848 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 849 dc->user_creatable = false; 850 } 851 852 static const TypeInfo sifive_u_soc_type_info = { 853 .name = TYPE_RISCV_U_SOC, 854 .parent = TYPE_DEVICE, 855 .instance_size = sizeof(SiFiveUSoCState), 856 .instance_init = sifive_u_soc_instance_init, 857 .class_init = sifive_u_soc_class_init, 858 }; 859 860 static void sifive_u_soc_register_types(void) 861 { 862 type_register_static(&sifive_u_soc_type_info); 863 } 864 865 type_init(sifive_u_soc_register_types) 866