1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 18 * This board currently generates devicetree dynamically that indicates at least 19 * two harts and up to five harts. 20 * 21 * This program is free software; you can redistribute it and/or modify it 22 * under the terms and conditions of the GNU General Public License, 23 * version 2 or later, as published by the Free Software Foundation. 24 * 25 * This program is distributed in the hope it will be useful, but WITHOUT 26 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 27 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 28 * more details. 29 * 30 * You should have received a copy of the GNU General Public License along with 31 * this program. If not, see <http://www.gnu.org/licenses/>. 32 */ 33 34 #include "qemu/osdep.h" 35 #include "qemu/log.h" 36 #include "qemu/error-report.h" 37 #include "qapi/error.h" 38 #include "qapi/visitor.h" 39 #include "hw/boards.h" 40 #include "hw/irq.h" 41 #include "hw/loader.h" 42 #include "hw/sysbus.h" 43 #include "hw/char/serial.h" 44 #include "hw/cpu/cluster.h" 45 #include "hw/misc/unimp.h" 46 #include "target/riscv/cpu.h" 47 #include "hw/riscv/riscv_hart.h" 48 #include "hw/riscv/sifive_plic.h" 49 #include "hw/riscv/sifive_clint.h" 50 #include "hw/riscv/sifive_uart.h" 51 #include "hw/riscv/sifive_u.h" 52 #include "hw/riscv/boot.h" 53 #include "chardev/char.h" 54 #include "net/eth.h" 55 #include "sysemu/arch_init.h" 56 #include "sysemu/device_tree.h" 57 #include "sysemu/runstate.h" 58 #include "sysemu/sysemu.h" 59 #include "exec/address-spaces.h" 60 61 #include <libfdt.h> 62 63 #if defined(TARGET_RISCV32) 64 # define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin" 65 #else 66 # define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" 67 #endif 68 69 static const struct MemmapEntry { 70 hwaddr base; 71 hwaddr size; 72 } sifive_u_memmap[] = { 73 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 74 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 75 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 76 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, 77 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 78 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, 79 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, 80 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, 81 [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 }, 82 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, 83 [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, 84 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 85 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, 86 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, 87 }; 88 89 #define OTP_SERIAL 1 90 #define GEM_REVISION 0x10070109 91 92 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 93 uint64_t mem_size, const char *cmdline) 94 { 95 MachineState *ms = MACHINE(qdev_get_machine()); 96 void *fdt; 97 int cpu; 98 uint32_t *cells; 99 char *nodename; 100 char ethclk_names[] = "pclk\0hclk"; 101 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 102 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 103 104 fdt = s->fdt = create_device_tree(&s->fdt_size); 105 if (!fdt) { 106 error_report("create_device_tree() failed"); 107 exit(1); 108 } 109 110 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 111 qemu_fdt_setprop_string(fdt, "/", "compatible", 112 "sifive,hifive-unleashed-a00"); 113 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 114 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 115 116 qemu_fdt_add_subnode(fdt, "/soc"); 117 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 118 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 119 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 120 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 121 122 hfclk_phandle = phandle++; 123 nodename = g_strdup_printf("/hfclk"); 124 qemu_fdt_add_subnode(fdt, nodename); 125 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 126 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 127 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 128 SIFIVE_U_HFCLK_FREQ); 129 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 130 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 131 g_free(nodename); 132 133 rtcclk_phandle = phandle++; 134 nodename = g_strdup_printf("/rtcclk"); 135 qemu_fdt_add_subnode(fdt, nodename); 136 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 137 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 138 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 139 SIFIVE_U_RTCCLK_FREQ); 140 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 141 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 142 g_free(nodename); 143 144 nodename = g_strdup_printf("/memory@%lx", 145 (long)memmap[SIFIVE_U_DRAM].base); 146 qemu_fdt_add_subnode(fdt, nodename); 147 qemu_fdt_setprop_cells(fdt, nodename, "reg", 148 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 149 mem_size >> 32, mem_size); 150 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 151 g_free(nodename); 152 153 qemu_fdt_add_subnode(fdt, "/cpus"); 154 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 155 SIFIVE_CLINT_TIMEBASE_FREQ); 156 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 157 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 158 159 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 160 int cpu_phandle = phandle++; 161 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 162 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 163 char *isa; 164 qemu_fdt_add_subnode(fdt, nodename); 165 /* cpu 0 is the management hart that does not have mmu */ 166 if (cpu != 0) { 167 #if defined(TARGET_RISCV32) 168 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 169 #else 170 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 171 #endif 172 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 173 } else { 174 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 175 } 176 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 177 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 178 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 179 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 180 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 181 qemu_fdt_add_subnode(fdt, intc); 182 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 183 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 184 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 185 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 186 g_free(isa); 187 g_free(intc); 188 g_free(nodename); 189 } 190 191 cells = g_new0(uint32_t, ms->smp.cpus * 4); 192 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 193 nodename = 194 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 195 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 196 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 197 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 198 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 199 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 200 g_free(nodename); 201 } 202 nodename = g_strdup_printf("/soc/clint@%lx", 203 (long)memmap[SIFIVE_U_CLINT].base); 204 qemu_fdt_add_subnode(fdt, nodename); 205 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 206 qemu_fdt_setprop_cells(fdt, nodename, "reg", 207 0x0, memmap[SIFIVE_U_CLINT].base, 208 0x0, memmap[SIFIVE_U_CLINT].size); 209 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 210 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 211 g_free(cells); 212 g_free(nodename); 213 214 nodename = g_strdup_printf("/soc/otp@%lx", 215 (long)memmap[SIFIVE_U_OTP].base); 216 qemu_fdt_add_subnode(fdt, nodename); 217 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 218 qemu_fdt_setprop_cells(fdt, nodename, "reg", 219 0x0, memmap[SIFIVE_U_OTP].base, 220 0x0, memmap[SIFIVE_U_OTP].size); 221 qemu_fdt_setprop_string(fdt, nodename, "compatible", 222 "sifive,fu540-c000-otp"); 223 g_free(nodename); 224 225 prci_phandle = phandle++; 226 nodename = g_strdup_printf("/soc/clock-controller@%lx", 227 (long)memmap[SIFIVE_U_PRCI].base); 228 qemu_fdt_add_subnode(fdt, nodename); 229 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 230 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 231 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 232 hfclk_phandle, rtcclk_phandle); 233 qemu_fdt_setprop_cells(fdt, nodename, "reg", 234 0x0, memmap[SIFIVE_U_PRCI].base, 235 0x0, memmap[SIFIVE_U_PRCI].size); 236 qemu_fdt_setprop_string(fdt, nodename, "compatible", 237 "sifive,fu540-c000-prci"); 238 g_free(nodename); 239 240 plic_phandle = phandle++; 241 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 242 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 243 nodename = 244 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 245 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 246 /* cpu 0 is the management hart that does not have S-mode */ 247 if (cpu == 0) { 248 cells[0] = cpu_to_be32(intc_phandle); 249 cells[1] = cpu_to_be32(IRQ_M_EXT); 250 } else { 251 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 252 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 253 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 254 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 255 } 256 g_free(nodename); 257 } 258 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 259 (long)memmap[SIFIVE_U_PLIC].base); 260 qemu_fdt_add_subnode(fdt, nodename); 261 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 262 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 263 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 264 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 265 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 266 qemu_fdt_setprop_cells(fdt, nodename, "reg", 267 0x0, memmap[SIFIVE_U_PLIC].base, 268 0x0, memmap[SIFIVE_U_PLIC].size); 269 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 270 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 271 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 272 g_free(cells); 273 g_free(nodename); 274 275 gpio_phandle = phandle++; 276 nodename = g_strdup_printf("/soc/gpio@%lx", 277 (long)memmap[SIFIVE_U_GPIO].base); 278 qemu_fdt_add_subnode(fdt, nodename); 279 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 280 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 281 prci_phandle, PRCI_CLK_TLCLK); 282 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 283 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 284 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 285 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 286 qemu_fdt_setprop_cells(fdt, nodename, "reg", 287 0x0, memmap[SIFIVE_U_GPIO].base, 288 0x0, memmap[SIFIVE_U_GPIO].size); 289 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 290 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 291 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 292 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 293 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 294 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 295 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 296 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 297 g_free(nodename); 298 299 nodename = g_strdup_printf("/gpio-restart"); 300 qemu_fdt_add_subnode(fdt, nodename); 301 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 302 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 303 g_free(nodename); 304 305 phy_phandle = phandle++; 306 nodename = g_strdup_printf("/soc/ethernet@%lx", 307 (long)memmap[SIFIVE_U_GEM].base); 308 qemu_fdt_add_subnode(fdt, nodename); 309 qemu_fdt_setprop_string(fdt, nodename, "compatible", 310 "sifive,fu540-c000-gem"); 311 qemu_fdt_setprop_cells(fdt, nodename, "reg", 312 0x0, memmap[SIFIVE_U_GEM].base, 313 0x0, memmap[SIFIVE_U_GEM].size, 314 0x0, memmap[SIFIVE_U_GEM_MGMT].base, 315 0x0, memmap[SIFIVE_U_GEM_MGMT].size); 316 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 317 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 318 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 319 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 320 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 321 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 322 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 323 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 324 sizeof(ethclk_names)); 325 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 326 s->soc.gem.conf.macaddr.a, ETH_ALEN); 327 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 328 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 329 330 qemu_fdt_add_subnode(fdt, "/aliases"); 331 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 332 333 g_free(nodename); 334 335 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 336 (long)memmap[SIFIVE_U_GEM].base); 337 qemu_fdt_add_subnode(fdt, nodename); 338 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 339 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 340 g_free(nodename); 341 342 nodename = g_strdup_printf("/soc/serial@%lx", 343 (long)memmap[SIFIVE_U_UART0].base); 344 qemu_fdt_add_subnode(fdt, nodename); 345 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 346 qemu_fdt_setprop_cells(fdt, nodename, "reg", 347 0x0, memmap[SIFIVE_U_UART0].base, 348 0x0, memmap[SIFIVE_U_UART0].size); 349 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 350 prci_phandle, PRCI_CLK_TLCLK); 351 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 352 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 353 354 qemu_fdt_add_subnode(fdt, "/chosen"); 355 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 356 if (cmdline) { 357 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 358 } 359 360 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 361 362 g_free(nodename); 363 } 364 365 static void sifive_u_machine_reset(void *opaque, int n, int level) 366 { 367 /* gpio pin active low triggers reset */ 368 if (!level) { 369 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 370 } 371 } 372 373 static void sifive_u_machine_init(MachineState *machine) 374 { 375 const struct MemmapEntry *memmap = sifive_u_memmap; 376 SiFiveUState *s = RISCV_U_MACHINE(machine); 377 MemoryRegion *system_memory = get_system_memory(); 378 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 379 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 380 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base; 381 int i; 382 383 /* Initialize SoC */ 384 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 385 object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", 386 &error_abort); 387 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 388 389 /* register RAM */ 390 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 391 machine->ram_size, &error_fatal); 392 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 393 main_mem); 394 395 /* register QSPI0 Flash */ 396 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 397 memmap[SIFIVE_U_FLASH0].size, &error_fatal); 398 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base, 399 flash0); 400 401 /* register gpio-restart */ 402 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 403 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 404 405 /* create device tree */ 406 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 407 408 riscv_find_and_load_firmware(machine, BIOS_FILENAME, 409 memmap[SIFIVE_U_DRAM].base, NULL); 410 411 if (machine->kernel_filename) { 412 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, 413 NULL); 414 415 if (machine->initrd_filename) { 416 hwaddr start; 417 hwaddr end = riscv_load_initrd(machine->initrd_filename, 418 machine->ram_size, kernel_entry, 419 &start); 420 qemu_fdt_setprop_cell(s->fdt, "/chosen", 421 "linux,initrd-start", start); 422 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 423 end); 424 } 425 } 426 427 if (s->start_in_flash) { 428 start_addr = memmap[SIFIVE_U_FLASH0].base; 429 } 430 431 /* reset vector */ 432 uint32_t reset_vec[8] = { 433 0x00000000, 434 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 435 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */ 436 0xf1402573, /* csrr a0, mhartid */ 437 #if defined(TARGET_RISCV32) 438 0x0182a283, /* lw t0, 24(t0) */ 439 #elif defined(TARGET_RISCV64) 440 0x0182e283, /* lwu t0, 24(t0) */ 441 #endif 442 0x00028067, /* jr t0 */ 443 0x00000000, 444 start_addr, /* start: .dword */ 445 /* dtb: */ 446 }; 447 448 /* copy in the reset vector in little_endian byte order */ 449 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 450 reset_vec[i] = cpu_to_le32(reset_vec[i]); 451 } 452 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 453 memmap[SIFIVE_U_MROM].base, &address_space_memory); 454 455 /* copy in the device tree */ 456 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 457 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 458 error_report("not enough space to store device-tree"); 459 exit(1); 460 } 461 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 462 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 463 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 464 &address_space_memory); 465 } 466 467 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 468 { 469 SiFiveUState *s = RISCV_U_MACHINE(obj); 470 471 return s->start_in_flash; 472 } 473 474 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 475 { 476 SiFiveUState *s = RISCV_U_MACHINE(obj); 477 478 s->start_in_flash = value; 479 } 480 481 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 482 const char *name, void *opaque, 483 Error **errp) 484 { 485 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 486 } 487 488 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 489 const char *name, void *opaque, 490 Error **errp) 491 { 492 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 493 } 494 495 static void sifive_u_machine_instance_init(Object *obj) 496 { 497 SiFiveUState *s = RISCV_U_MACHINE(obj); 498 499 s->start_in_flash = false; 500 object_property_add_bool(obj, "start-in-flash", 501 sifive_u_machine_get_start_in_flash, 502 sifive_u_machine_set_start_in_flash); 503 object_property_set_description(obj, "start-in-flash", 504 "Set on to tell QEMU's ROM to jump to " 505 "flash. Otherwise QEMU will jump to DRAM"); 506 507 s->msel = 0; 508 object_property_add(obj, "msel", "uint32", 509 sifive_u_machine_get_uint32_prop, 510 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 511 object_property_set_description(obj, "msel", 512 "Mode Select (MSEL[3:0]) pin state"); 513 514 s->serial = OTP_SERIAL; 515 object_property_add(obj, "serial", "uint32", 516 sifive_u_machine_get_uint32_prop, 517 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 518 object_property_set_description(obj, "serial", "Board serial number"); 519 } 520 521 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 522 { 523 MachineClass *mc = MACHINE_CLASS(oc); 524 525 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 526 mc->init = sifive_u_machine_init; 527 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 528 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 529 mc->default_cpus = mc->min_cpus; 530 } 531 532 static const TypeInfo sifive_u_machine_typeinfo = { 533 .name = MACHINE_TYPE_NAME("sifive_u"), 534 .parent = TYPE_MACHINE, 535 .class_init = sifive_u_machine_class_init, 536 .instance_init = sifive_u_machine_instance_init, 537 .instance_size = sizeof(SiFiveUState), 538 }; 539 540 static void sifive_u_machine_init_register_types(void) 541 { 542 type_register_static(&sifive_u_machine_typeinfo); 543 } 544 545 type_init(sifive_u_machine_init_register_types) 546 547 static void sifive_u_soc_instance_init(Object *obj) 548 { 549 MachineState *ms = MACHINE(qdev_get_machine()); 550 SiFiveUSoCState *s = RISCV_U_SOC(obj); 551 552 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 553 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 554 555 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 556 TYPE_RISCV_HART_ARRAY); 557 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 558 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 559 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 560 561 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 562 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 563 564 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 565 TYPE_RISCV_HART_ARRAY); 566 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 567 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 568 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); 569 570 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 571 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 572 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 573 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 574 } 575 576 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 577 { 578 MachineState *ms = MACHINE(qdev_get_machine()); 579 SiFiveUSoCState *s = RISCV_U_SOC(dev); 580 const struct MemmapEntry *memmap = sifive_u_memmap; 581 MemoryRegion *system_memory = get_system_memory(); 582 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 583 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 584 char *plic_hart_config; 585 size_t plic_hart_config_len; 586 int i; 587 Error *err = NULL; 588 NICInfo *nd = &nd_table[0]; 589 590 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 591 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 592 /* 593 * The cluster must be realized after the RISC-V hart array container, 594 * as the container's CPU object is only created on realize, and the 595 * CPU must exist and have been parented into the cluster before the 596 * cluster is realized. 597 */ 598 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 599 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 600 601 /* boot rom */ 602 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 603 memmap[SIFIVE_U_MROM].size, &error_fatal); 604 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 605 mask_rom); 606 607 /* 608 * Add L2-LIM at reset size. 609 * This should be reduced in size as the L2 Cache Controller WayEnable 610 * register is incremented. Unfortunately I don't see a nice (or any) way 611 * to handle reducing or blocking out the L2 LIM while still allowing it 612 * be re returned to all enabled after a reset. For the time being, just 613 * leave it enabled all the time. This won't break anything, but will be 614 * too generous to misbehaving guests. 615 */ 616 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 617 memmap[SIFIVE_U_L2LIM].size, &error_fatal); 618 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, 619 l2lim_mem); 620 621 /* create PLIC hart topology configuration string */ 622 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 623 ms->smp.cpus; 624 plic_hart_config = g_malloc0(plic_hart_config_len); 625 for (i = 0; i < ms->smp.cpus; i++) { 626 if (i != 0) { 627 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 628 plic_hart_config_len); 629 } else { 630 strncat(plic_hart_config, "M", plic_hart_config_len); 631 } 632 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 633 } 634 635 /* MMIO */ 636 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 637 plic_hart_config, 638 SIFIVE_U_PLIC_NUM_SOURCES, 639 SIFIVE_U_PLIC_NUM_PRIORITIES, 640 SIFIVE_U_PLIC_PRIORITY_BASE, 641 SIFIVE_U_PLIC_PENDING_BASE, 642 SIFIVE_U_PLIC_ENABLE_BASE, 643 SIFIVE_U_PLIC_ENABLE_STRIDE, 644 SIFIVE_U_PLIC_CONTEXT_BASE, 645 SIFIVE_U_PLIC_CONTEXT_STRIDE, 646 memmap[SIFIVE_U_PLIC].size); 647 g_free(plic_hart_config); 648 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 649 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 650 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 651 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 652 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 653 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 654 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); 655 656 sysbus_realize(SYS_BUS_DEVICE(&s->prci), &err); 657 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); 658 659 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 660 sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err); 661 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base); 662 663 /* Pass all GPIOs to the SOC layer so they are available to the board */ 664 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 665 666 /* Connect GPIO interrupts to the PLIC */ 667 for (i = 0; i < 16; i++) { 668 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 669 qdev_get_gpio_in(DEVICE(s->plic), 670 SIFIVE_U_GPIO_IRQ0 + i)); 671 } 672 673 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 674 sysbus_realize(SYS_BUS_DEVICE(&s->otp), &err); 675 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); 676 677 if (nd->used) { 678 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 679 qdev_set_nic_properties(DEVICE(&s->gem), nd); 680 } 681 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 682 &error_abort); 683 sysbus_realize(SYS_BUS_DEVICE(&s->gem), &err); 684 if (err) { 685 error_propagate(errp, err); 686 return; 687 } 688 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 689 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 690 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 691 692 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 693 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); 694 } 695 696 static Property sifive_u_soc_props[] = { 697 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 698 DEFINE_PROP_END_OF_LIST() 699 }; 700 701 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 702 { 703 DeviceClass *dc = DEVICE_CLASS(oc); 704 705 device_class_set_props(dc, sifive_u_soc_props); 706 dc->realize = sifive_u_soc_realize; 707 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 708 dc->user_creatable = false; 709 } 710 711 static const TypeInfo sifive_u_soc_type_info = { 712 .name = TYPE_RISCV_U_SOC, 713 .parent = TYPE_DEVICE, 714 .instance_size = sizeof(SiFiveUSoCState), 715 .instance_init = sifive_u_soc_instance_init, 716 .class_init = sifive_u_soc_class_init, 717 }; 718 719 static void sifive_u_soc_register_types(void) 720 { 721 type_register_static(&sifive_u_soc_type_info); 722 } 723 724 type_init(sifive_u_soc_register_types) 725