1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * 7 * Provides a board compatible with the SiFive Freedom U SDK: 8 * 9 * 0) UART 10 * 1) CLINT (Core Level Interruptor) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This board currently uses a hardcoded devicetree that indicates one hart. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms and conditions of the GNU General Public License, 17 * version 2 or later, as published by the Free Software Foundation. 18 * 19 * This program is distributed in the hope it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 22 * more details. 23 * 24 * You should have received a copy of the GNU General Public License along with 25 * this program. If not, see <http://www.gnu.org/licenses/>. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "qapi/error.h" 32 #include "hw/hw.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/sysbus.h" 36 #include "hw/char/serial.h" 37 #include "target/riscv/cpu.h" 38 #include "hw/riscv/riscv_hart.h" 39 #include "hw/riscv/sifive_plic.h" 40 #include "hw/riscv/sifive_clint.h" 41 #include "hw/riscv/sifive_uart.h" 42 #include "hw/riscv/sifive_prci.h" 43 #include "hw/riscv/sifive_u.h" 44 #include "chardev/char.h" 45 #include "sysemu/arch_init.h" 46 #include "sysemu/device_tree.h" 47 #include "exec/address-spaces.h" 48 #include "elf.h" 49 50 #include <libfdt.h> 51 52 static const struct MemmapEntry { 53 hwaddr base; 54 hwaddr size; 55 } sifive_u_memmap[] = { 56 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 57 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 58 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 59 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 60 [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, 61 [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, 62 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 63 [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, 64 }; 65 66 #define GEM_REVISION 0x10070109 67 68 static target_ulong load_kernel(const char *kernel_filename) 69 { 70 uint64_t kernel_entry, kernel_high; 71 72 if (load_elf(kernel_filename, NULL, NULL, NULL, 73 &kernel_entry, NULL, &kernel_high, 74 0, EM_RISCV, 1, 0) < 0) { 75 error_report("could not load kernel '%s'", kernel_filename); 76 exit(1); 77 } 78 return kernel_entry; 79 } 80 81 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 82 uint64_t mem_size, const char *cmdline) 83 { 84 void *fdt; 85 int cpu; 86 uint32_t *cells; 87 char *nodename; 88 char ethclk_names[] = "pclk\0hclk\0tx_clk"; 89 uint32_t plic_phandle, ethclk_phandle; 90 91 fdt = s->fdt = create_device_tree(&s->fdt_size); 92 if (!fdt) { 93 error_report("create_device_tree() failed"); 94 exit(1); 95 } 96 97 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 98 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 99 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 100 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 101 102 qemu_fdt_add_subnode(fdt, "/soc"); 103 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 104 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 105 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 106 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 107 108 nodename = g_strdup_printf("/memory@%lx", 109 (long)memmap[SIFIVE_U_DRAM].base); 110 qemu_fdt_add_subnode(fdt, nodename); 111 qemu_fdt_setprop_cells(fdt, nodename, "reg", 112 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 113 mem_size >> 32, mem_size); 114 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 115 g_free(nodename); 116 117 qemu_fdt_add_subnode(fdt, "/cpus"); 118 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 119 SIFIVE_CLINT_TIMEBASE_FREQ); 120 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 121 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 122 123 for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { 124 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 125 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 126 char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); 127 qemu_fdt_add_subnode(fdt, nodename); 128 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 129 SIFIVE_U_CLOCK_FREQ); 130 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 131 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 132 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 133 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 134 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 135 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 136 qemu_fdt_add_subnode(fdt, intc); 137 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); 138 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); 139 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 140 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 141 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 142 g_free(isa); 143 g_free(intc); 144 g_free(nodename); 145 } 146 147 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 148 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 149 nodename = 150 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 151 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 152 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 153 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 154 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 155 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 156 g_free(nodename); 157 } 158 nodename = g_strdup_printf("/soc/clint@%lx", 159 (long)memmap[SIFIVE_U_CLINT].base); 160 qemu_fdt_add_subnode(fdt, nodename); 161 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 162 qemu_fdt_setprop_cells(fdt, nodename, "reg", 163 0x0, memmap[SIFIVE_U_CLINT].base, 164 0x0, memmap[SIFIVE_U_CLINT].size); 165 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 166 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 167 g_free(cells); 168 g_free(nodename); 169 170 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 171 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 172 nodename = 173 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 174 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 175 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 176 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 177 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 178 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 179 g_free(nodename); 180 } 181 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 182 (long)memmap[SIFIVE_U_PLIC].base); 183 qemu_fdt_add_subnode(fdt, nodename); 184 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 185 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 186 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 187 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 188 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 189 qemu_fdt_setprop_cells(fdt, nodename, "reg", 190 0x0, memmap[SIFIVE_U_PLIC].base, 191 0x0, memmap[SIFIVE_U_PLIC].size); 192 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 193 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); 194 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 195 qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2); 196 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2); 197 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 198 g_free(cells); 199 g_free(nodename); 200 201 nodename = g_strdup_printf("/soc/ethclk"); 202 qemu_fdt_add_subnode(fdt, nodename); 203 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 204 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 205 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 206 SIFIVE_U_GEM_CLOCK_FREQ); 207 qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3); 208 qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3); 209 ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); 210 g_free(nodename); 211 212 nodename = g_strdup_printf("/soc/ethernet@%lx", 213 (long)memmap[SIFIVE_U_GEM].base); 214 qemu_fdt_add_subnode(fdt, nodename); 215 qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); 216 qemu_fdt_setprop_cells(fdt, nodename, "reg", 217 0x0, memmap[SIFIVE_U_GEM].base, 218 0x0, memmap[SIFIVE_U_GEM].size); 219 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 220 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 221 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 222 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 223 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 224 ethclk_phandle, ethclk_phandle, ethclk_phandle); 225 qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, 226 sizeof(ethclk_names)); 227 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); 228 qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); 229 g_free(nodename); 230 231 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 232 (long)memmap[SIFIVE_U_GEM].base); 233 qemu_fdt_add_subnode(fdt, nodename); 234 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); 235 g_free(nodename); 236 237 nodename = g_strdup_printf("/soc/uart@%lx", 238 (long)memmap[SIFIVE_U_UART0].base); 239 qemu_fdt_add_subnode(fdt, nodename); 240 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 241 qemu_fdt_setprop_cells(fdt, nodename, "reg", 242 0x0, memmap[SIFIVE_U_UART0].base, 243 0x0, memmap[SIFIVE_U_UART0].size); 244 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 245 SIFIVE_U_CLOCK_FREQ / 2); 246 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 247 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 248 249 qemu_fdt_add_subnode(fdt, "/chosen"); 250 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 251 if (cmdline) { 252 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 253 } 254 g_free(nodename); 255 } 256 257 static void riscv_sifive_u_init(MachineState *machine) 258 { 259 const struct MemmapEntry *memmap = sifive_u_memmap; 260 261 SiFiveUState *s = g_new0(SiFiveUState, 1); 262 MemoryRegion *system_memory = get_system_memory(); 263 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 264 int i; 265 266 /* Initialize SoC */ 267 object_initialize_child(OBJECT(machine), "soc", &s->soc, 268 sizeof(s->soc), TYPE_RISCV_U_SOC, 269 &error_abort, NULL); 270 object_property_set_bool(OBJECT(&s->soc), true, "realized", 271 &error_abort); 272 273 /* register RAM */ 274 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 275 machine->ram_size, &error_fatal); 276 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 277 main_mem); 278 279 /* create device tree */ 280 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 281 282 if (machine->kernel_filename) { 283 load_kernel(machine->kernel_filename); 284 } 285 286 /* reset vector */ 287 uint32_t reset_vec[8] = { 288 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 289 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 290 0xf1402573, /* csrr a0, mhartid */ 291 #if defined(TARGET_RISCV32) 292 0x0182a283, /* lw t0, 24(t0) */ 293 #elif defined(TARGET_RISCV64) 294 0x0182b283, /* ld t0, 24(t0) */ 295 #endif 296 0x00028067, /* jr t0 */ 297 0x00000000, 298 memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ 299 0x00000000, 300 /* dtb: */ 301 }; 302 303 /* copy in the reset vector in little_endian byte order */ 304 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 305 reset_vec[i] = cpu_to_le32(reset_vec[i]); 306 } 307 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 308 memmap[SIFIVE_U_MROM].base, &address_space_memory); 309 310 /* copy in the device tree */ 311 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 312 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 313 error_report("not enough space to store device-tree"); 314 exit(1); 315 } 316 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 317 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 318 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 319 &address_space_memory); 320 } 321 322 static void riscv_sifive_u_soc_init(Object *obj) 323 { 324 SiFiveUSoCState *s = RISCV_U_SOC(obj); 325 326 object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), 327 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 328 object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", 329 &error_abort); 330 object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", 331 &error_abort); 332 333 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), 334 TYPE_CADENCE_GEM); 335 } 336 337 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 338 { 339 SiFiveUSoCState *s = RISCV_U_SOC(dev); 340 const struct MemmapEntry *memmap = sifive_u_memmap; 341 MemoryRegion *system_memory = get_system_memory(); 342 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 343 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; 344 int i; 345 Error *err = NULL; 346 NICInfo *nd = &nd_table[0]; 347 348 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 349 &error_abort); 350 351 /* boot rom */ 352 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", 353 memmap[SIFIVE_U_MROM].size, &error_fatal); 354 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 355 mask_rom); 356 357 /* MMIO */ 358 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 359 (char *)SIFIVE_U_PLIC_HART_CONFIG, 360 SIFIVE_U_PLIC_NUM_SOURCES, 361 SIFIVE_U_PLIC_NUM_PRIORITIES, 362 SIFIVE_U_PLIC_PRIORITY_BASE, 363 SIFIVE_U_PLIC_PENDING_BASE, 364 SIFIVE_U_PLIC_ENABLE_BASE, 365 SIFIVE_U_PLIC_ENABLE_STRIDE, 366 SIFIVE_U_PLIC_CONTEXT_BASE, 367 SIFIVE_U_PLIC_CONTEXT_STRIDE, 368 memmap[SIFIVE_U_PLIC].size); 369 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 370 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 371 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 372 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 373 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 374 memmap[SIFIVE_U_CLINT].size, smp_cpus, 375 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 376 377 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { 378 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); 379 } 380 381 if (nd->used) { 382 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 383 qdev_set_nic_properties(DEVICE(&s->gem), nd); 384 } 385 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 386 &error_abort); 387 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); 388 if (err) { 389 error_propagate(errp, err); 390 return; 391 } 392 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 393 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 394 plic_gpios[SIFIVE_U_GEM_IRQ]); 395 } 396 397 static void riscv_sifive_u_machine_init(MachineClass *mc) 398 { 399 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 400 mc->init = riscv_sifive_u_init; 401 /* The real hardware has 5 CPUs, but one of them is a small embedded power 402 * management CPU. 403 */ 404 mc->max_cpus = 4; 405 } 406 407 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) 408 409 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 410 { 411 DeviceClass *dc = DEVICE_CLASS(oc); 412 413 dc->realize = riscv_sifive_u_soc_realize; 414 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 415 dc->user_creatable = false; 416 } 417 418 static const TypeInfo riscv_sifive_u_soc_type_info = { 419 .name = TYPE_RISCV_U_SOC, 420 .parent = TYPE_DEVICE, 421 .instance_size = sizeof(SiFiveUSoCState), 422 .instance_init = riscv_sifive_u_soc_init, 423 .class_init = riscv_sifive_u_soc_class_init, 424 }; 425 426 static void riscv_sifive_u_soc_register_types(void) 427 { 428 type_register_static(&riscv_sifive_u_soc_type_info); 429 } 430 431 type_init(riscv_sifive_u_soc_register_types) 432