1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 8) SPI0 connected to an SPI flash 19 * 9) SPI2 connected to an SD card 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qapi/error.h" 40 #include "qapi/visitor.h" 41 #include "hw/boards.h" 42 #include "hw/irq.h" 43 #include "hw/loader.h" 44 #include "hw/sysbus.h" 45 #include "hw/char/serial.h" 46 #include "hw/cpu/cluster.h" 47 #include "hw/misc/unimp.h" 48 #include "hw/ssi/ssi.h" 49 #include "target/riscv/cpu.h" 50 #include "hw/riscv/riscv_hart.h" 51 #include "hw/riscv/sifive_u.h" 52 #include "hw/riscv/boot.h" 53 #include "hw/char/sifive_uart.h" 54 #include "hw/intc/sifive_clint.h" 55 #include "hw/intc/sifive_plic.h" 56 #include "chardev/char.h" 57 #include "net/eth.h" 58 #include "sysemu/arch_init.h" 59 #include "sysemu/device_tree.h" 60 #include "sysemu/runstate.h" 61 #include "sysemu/sysemu.h" 62 63 #include <libfdt.h> 64 65 /* CLINT timebase frequency */ 66 #define CLINT_TIMEBASE_FREQ 1000000 67 68 static const MemMapEntry sifive_u_memmap[] = { 69 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 70 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 71 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 72 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 73 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 74 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 75 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 76 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 77 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 78 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 79 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, 80 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, 81 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 82 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 83 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 84 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 85 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 86 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 87 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 88 }; 89 90 #define OTP_SERIAL 1 91 #define GEM_REVISION 0x10070109 92 93 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, 94 uint64_t mem_size, const char *cmdline, bool is_32_bit) 95 { 96 MachineState *ms = MACHINE(qdev_get_machine()); 97 void *fdt; 98 int cpu; 99 uint32_t *cells; 100 char *nodename; 101 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 102 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 103 static const char * const ethclk_names[2] = { "pclk", "hclk" }; 104 static const char * const clint_compat[2] = { 105 "sifive,clint0", "riscv,clint0" 106 }; 107 static const char * const plic_compat[2] = { 108 "sifive,plic-1.0.0", "riscv,plic0" 109 }; 110 111 if (ms->dtb) { 112 fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); 113 if (!fdt) { 114 error_report("load_device_tree() failed"); 115 exit(1); 116 } 117 goto update_bootargs; 118 } else { 119 fdt = s->fdt = create_device_tree(&s->fdt_size); 120 if (!fdt) { 121 error_report("create_device_tree() failed"); 122 exit(1); 123 } 124 } 125 126 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 127 qemu_fdt_setprop_string(fdt, "/", "compatible", 128 "sifive,hifive-unleashed-a00"); 129 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 130 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 131 132 qemu_fdt_add_subnode(fdt, "/soc"); 133 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 134 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 135 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 136 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 137 138 hfclk_phandle = phandle++; 139 nodename = g_strdup_printf("/hfclk"); 140 qemu_fdt_add_subnode(fdt, nodename); 141 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 142 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 143 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 144 SIFIVE_U_HFCLK_FREQ); 145 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 146 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 147 g_free(nodename); 148 149 rtcclk_phandle = phandle++; 150 nodename = g_strdup_printf("/rtcclk"); 151 qemu_fdt_add_subnode(fdt, nodename); 152 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 153 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 154 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 155 SIFIVE_U_RTCCLK_FREQ); 156 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 157 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 158 g_free(nodename); 159 160 nodename = g_strdup_printf("/memory@%lx", 161 (long)memmap[SIFIVE_U_DEV_DRAM].base); 162 qemu_fdt_add_subnode(fdt, nodename); 163 qemu_fdt_setprop_cells(fdt, nodename, "reg", 164 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 165 mem_size >> 32, mem_size); 166 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 167 g_free(nodename); 168 169 qemu_fdt_add_subnode(fdt, "/cpus"); 170 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 171 CLINT_TIMEBASE_FREQ); 172 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 173 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 174 175 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 176 int cpu_phandle = phandle++; 177 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 178 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 179 char *isa; 180 qemu_fdt_add_subnode(fdt, nodename); 181 /* cpu 0 is the management hart that does not have mmu */ 182 if (cpu != 0) { 183 if (is_32_bit) { 184 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 185 } else { 186 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 187 } 188 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 189 } else { 190 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 191 } 192 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 193 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 194 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 195 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 196 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 197 qemu_fdt_add_subnode(fdt, intc); 198 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 199 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 200 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 201 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 202 g_free(isa); 203 g_free(intc); 204 g_free(nodename); 205 } 206 207 cells = g_new0(uint32_t, ms->smp.cpus * 4); 208 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 209 nodename = 210 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 211 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 212 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 213 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 214 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 215 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 216 g_free(nodename); 217 } 218 nodename = g_strdup_printf("/soc/clint@%lx", 219 (long)memmap[SIFIVE_U_DEV_CLINT].base); 220 qemu_fdt_add_subnode(fdt, nodename); 221 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 222 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 223 qemu_fdt_setprop_cells(fdt, nodename, "reg", 224 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 225 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 226 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 227 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 228 g_free(cells); 229 g_free(nodename); 230 231 nodename = g_strdup_printf("/soc/otp@%lx", 232 (long)memmap[SIFIVE_U_DEV_OTP].base); 233 qemu_fdt_add_subnode(fdt, nodename); 234 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 235 qemu_fdt_setprop_cells(fdt, nodename, "reg", 236 0x0, memmap[SIFIVE_U_DEV_OTP].base, 237 0x0, memmap[SIFIVE_U_DEV_OTP].size); 238 qemu_fdt_setprop_string(fdt, nodename, "compatible", 239 "sifive,fu540-c000-otp"); 240 g_free(nodename); 241 242 prci_phandle = phandle++; 243 nodename = g_strdup_printf("/soc/clock-controller@%lx", 244 (long)memmap[SIFIVE_U_DEV_PRCI].base); 245 qemu_fdt_add_subnode(fdt, nodename); 246 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 247 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 248 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 249 hfclk_phandle, rtcclk_phandle); 250 qemu_fdt_setprop_cells(fdt, nodename, "reg", 251 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 252 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 253 qemu_fdt_setprop_string(fdt, nodename, "compatible", 254 "sifive,fu540-c000-prci"); 255 g_free(nodename); 256 257 plic_phandle = phandle++; 258 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 259 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 260 nodename = 261 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 262 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 263 /* cpu 0 is the management hart that does not have S-mode */ 264 if (cpu == 0) { 265 cells[0] = cpu_to_be32(intc_phandle); 266 cells[1] = cpu_to_be32(IRQ_M_EXT); 267 } else { 268 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 269 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 270 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 271 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 272 } 273 g_free(nodename); 274 } 275 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 276 (long)memmap[SIFIVE_U_DEV_PLIC].base); 277 qemu_fdt_add_subnode(fdt, nodename); 278 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 279 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 280 (char **)&plic_compat, ARRAY_SIZE(plic_compat)); 281 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 282 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 283 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 284 qemu_fdt_setprop_cells(fdt, nodename, "reg", 285 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 286 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 287 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 288 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 289 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 290 g_free(cells); 291 g_free(nodename); 292 293 gpio_phandle = phandle++; 294 nodename = g_strdup_printf("/soc/gpio@%lx", 295 (long)memmap[SIFIVE_U_DEV_GPIO].base); 296 qemu_fdt_add_subnode(fdt, nodename); 297 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 298 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 299 prci_phandle, PRCI_CLK_TLCLK); 300 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 301 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 302 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 303 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 304 qemu_fdt_setprop_cells(fdt, nodename, "reg", 305 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 306 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 307 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 308 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 309 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 310 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 311 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 312 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 313 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 314 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 315 g_free(nodename); 316 317 nodename = g_strdup_printf("/gpio-restart"); 318 qemu_fdt_add_subnode(fdt, nodename); 319 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 320 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 321 g_free(nodename); 322 323 nodename = g_strdup_printf("/soc/dma@%lx", 324 (long)memmap[SIFIVE_U_DEV_PDMA].base); 325 qemu_fdt_add_subnode(fdt, nodename); 326 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 327 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 328 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 329 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 330 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 331 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 332 qemu_fdt_setprop_cells(fdt, nodename, "reg", 333 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 334 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 335 qemu_fdt_setprop_string(fdt, nodename, "compatible", 336 "sifive,fu540-c000-pdma"); 337 g_free(nodename); 338 339 nodename = g_strdup_printf("/soc/cache-controller@%lx", 340 (long)memmap[SIFIVE_U_DEV_L2CC].base); 341 qemu_fdt_add_subnode(fdt, nodename); 342 qemu_fdt_setprop_cells(fdt, nodename, "reg", 343 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 344 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 345 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 346 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 347 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 348 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 349 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 350 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 351 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 352 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 353 qemu_fdt_setprop_string(fdt, nodename, "compatible", 354 "sifive,fu540-c000-ccache"); 355 g_free(nodename); 356 357 nodename = g_strdup_printf("/soc/spi@%lx", 358 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 359 qemu_fdt_add_subnode(fdt, nodename); 360 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 361 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 362 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 363 prci_phandle, PRCI_CLK_TLCLK); 364 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); 365 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 366 qemu_fdt_setprop_cells(fdt, nodename, "reg", 367 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, 368 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); 369 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 370 g_free(nodename); 371 372 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", 373 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 374 qemu_fdt_add_subnode(fdt, nodename); 375 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); 376 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); 377 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); 378 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 379 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); 380 g_free(nodename); 381 382 nodename = g_strdup_printf("/soc/spi@%lx", 383 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 384 qemu_fdt_add_subnode(fdt, nodename); 385 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 386 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 387 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 388 prci_phandle, PRCI_CLK_TLCLK); 389 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); 390 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 391 qemu_fdt_setprop_cells(fdt, nodename, "reg", 392 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, 393 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); 394 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 395 g_free(nodename); 396 397 nodename = g_strdup_printf("/soc/spi@%lx/flash@0", 398 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 399 qemu_fdt_add_subnode(fdt, nodename); 400 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); 401 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); 402 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); 403 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); 404 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 405 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); 406 g_free(nodename); 407 408 phy_phandle = phandle++; 409 nodename = g_strdup_printf("/soc/ethernet@%lx", 410 (long)memmap[SIFIVE_U_DEV_GEM].base); 411 qemu_fdt_add_subnode(fdt, nodename); 412 qemu_fdt_setprop_string(fdt, nodename, "compatible", 413 "sifive,fu540-c000-gem"); 414 qemu_fdt_setprop_cells(fdt, nodename, "reg", 415 0x0, memmap[SIFIVE_U_DEV_GEM].base, 416 0x0, memmap[SIFIVE_U_DEV_GEM].size, 417 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 418 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 419 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 420 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 421 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 422 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 423 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 424 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 425 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 426 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", 427 (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); 428 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 429 s->soc.gem.conf.macaddr.a, ETH_ALEN); 430 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 431 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 432 433 qemu_fdt_add_subnode(fdt, "/aliases"); 434 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 435 436 g_free(nodename); 437 438 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 439 (long)memmap[SIFIVE_U_DEV_GEM].base); 440 qemu_fdt_add_subnode(fdt, nodename); 441 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 442 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 443 g_free(nodename); 444 445 nodename = g_strdup_printf("/soc/serial@%lx", 446 (long)memmap[SIFIVE_U_DEV_UART1].base); 447 qemu_fdt_add_subnode(fdt, nodename); 448 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 449 qemu_fdt_setprop_cells(fdt, nodename, "reg", 450 0x0, memmap[SIFIVE_U_DEV_UART1].base, 451 0x0, memmap[SIFIVE_U_DEV_UART1].size); 452 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 453 prci_phandle, PRCI_CLK_TLCLK); 454 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 455 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); 456 457 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); 458 g_free(nodename); 459 460 nodename = g_strdup_printf("/soc/serial@%lx", 461 (long)memmap[SIFIVE_U_DEV_UART0].base); 462 qemu_fdt_add_subnode(fdt, nodename); 463 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 464 qemu_fdt_setprop_cells(fdt, nodename, "reg", 465 0x0, memmap[SIFIVE_U_DEV_UART0].base, 466 0x0, memmap[SIFIVE_U_DEV_UART0].size); 467 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 468 prci_phandle, PRCI_CLK_TLCLK); 469 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 470 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 471 472 qemu_fdt_add_subnode(fdt, "/chosen"); 473 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 474 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 475 476 g_free(nodename); 477 478 update_bootargs: 479 if (cmdline) { 480 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 481 } 482 } 483 484 static void sifive_u_machine_reset(void *opaque, int n, int level) 485 { 486 /* gpio pin active low triggers reset */ 487 if (!level) { 488 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 489 } 490 } 491 492 static void sifive_u_machine_init(MachineState *machine) 493 { 494 const MemMapEntry *memmap = sifive_u_memmap; 495 SiFiveUState *s = RISCV_U_MACHINE(machine); 496 MemoryRegion *system_memory = get_system_memory(); 497 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 498 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 499 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 500 target_ulong firmware_end_addr, kernel_start_addr; 501 uint32_t start_addr_hi32 = 0x00000000; 502 int i; 503 uint32_t fdt_load_addr; 504 uint64_t kernel_entry; 505 DriveInfo *dinfo; 506 DeviceState *flash_dev, *sd_dev; 507 qemu_irq flash_cs, sd_cs; 508 509 /* Initialize SoC */ 510 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 511 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 512 &error_abort); 513 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 514 &error_abort); 515 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 516 517 /* register RAM */ 518 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 519 machine->ram_size, &error_fatal); 520 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 521 main_mem); 522 523 /* register QSPI0 Flash */ 524 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 525 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 526 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 527 flash0); 528 529 /* register gpio-restart */ 530 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 531 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 532 533 /* create device tree */ 534 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 535 riscv_is_32bit(&s->soc.u_cpus)); 536 537 if (s->start_in_flash) { 538 /* 539 * If start_in_flash property is given, assign s->msel to a value 540 * that representing booting from QSPI0 memory-mapped flash. 541 * 542 * This also means that when both start_in_flash and msel properties 543 * are given, start_in_flash takes the precedence over msel. 544 * 545 * Note this is to keep backward compatibility not to break existing 546 * users that use start_in_flash property. 547 */ 548 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 549 } 550 551 switch (s->msel) { 552 case MSEL_MEMMAP_QSPI0_FLASH: 553 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 554 break; 555 case MSEL_L2LIM_QSPI0_FLASH: 556 case MSEL_L2LIM_QSPI2_SD: 557 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 558 break; 559 default: 560 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 561 break; 562 } 563 564 if (riscv_is_32bit(&s->soc.u_cpus)) { 565 firmware_end_addr = riscv_find_and_load_firmware(machine, 566 RISCV32_BIOS_BIN, start_addr, NULL); 567 } else { 568 firmware_end_addr = riscv_find_and_load_firmware(machine, 569 RISCV64_BIOS_BIN, start_addr, NULL); 570 } 571 572 if (machine->kernel_filename) { 573 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 574 firmware_end_addr); 575 576 kernel_entry = riscv_load_kernel(machine->kernel_filename, 577 kernel_start_addr, NULL); 578 579 if (machine->initrd_filename) { 580 hwaddr start; 581 hwaddr end = riscv_load_initrd(machine->initrd_filename, 582 machine->ram_size, kernel_entry, 583 &start); 584 qemu_fdt_setprop_cell(s->fdt, "/chosen", 585 "linux,initrd-start", start); 586 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 587 end); 588 } 589 } else { 590 /* 591 * If dynamic firmware is used, it doesn't know where is the next mode 592 * if kernel argument is not set. 593 */ 594 kernel_entry = 0; 595 } 596 597 /* Compute the fdt load address in dram */ 598 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, 599 machine->ram_size, s->fdt); 600 if (!riscv_is_32bit(&s->soc.u_cpus)) { 601 start_addr_hi32 = (uint64_t)start_addr >> 32; 602 } 603 604 /* reset vector */ 605 uint32_t reset_vec[12] = { 606 s->msel, /* MSEL pin state */ 607 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 608 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ 609 0xf1402573, /* csrr a0, mhartid */ 610 0, 611 0, 612 0x00028067, /* jr t0 */ 613 start_addr, /* start: .dword */ 614 start_addr_hi32, 615 fdt_load_addr, /* fdt_laddr: .dword */ 616 0x00000000, 617 0x00000000, 618 /* fw_dyn: */ 619 }; 620 if (riscv_is_32bit(&s->soc.u_cpus)) { 621 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ 622 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ 623 } else { 624 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ 625 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ 626 } 627 628 629 /* copy in the reset vector in little_endian byte order */ 630 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 631 reset_vec[i] = cpu_to_le32(reset_vec[i]); 632 } 633 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 634 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 635 636 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, 637 memmap[SIFIVE_U_DEV_MROM].size, 638 sizeof(reset_vec), kernel_entry); 639 640 /* Connect an SPI flash to SPI0 */ 641 flash_dev = qdev_new("is25wp256"); 642 dinfo = drive_get_next(IF_MTD); 643 if (dinfo) { 644 qdev_prop_set_drive_err(flash_dev, "drive", 645 blk_by_legacy_dinfo(dinfo), 646 &error_fatal); 647 } 648 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); 649 650 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 651 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); 652 653 /* Connect an SD card to SPI2 */ 654 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); 655 656 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); 657 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); 658 } 659 660 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 661 { 662 SiFiveUState *s = RISCV_U_MACHINE(obj); 663 664 return s->start_in_flash; 665 } 666 667 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 668 { 669 SiFiveUState *s = RISCV_U_MACHINE(obj); 670 671 s->start_in_flash = value; 672 } 673 674 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 675 const char *name, void *opaque, 676 Error **errp) 677 { 678 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 679 } 680 681 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 682 const char *name, void *opaque, 683 Error **errp) 684 { 685 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 686 } 687 688 static void sifive_u_machine_instance_init(Object *obj) 689 { 690 SiFiveUState *s = RISCV_U_MACHINE(obj); 691 692 s->start_in_flash = false; 693 s->msel = 0; 694 object_property_add(obj, "msel", "uint32", 695 sifive_u_machine_get_uint32_prop, 696 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 697 object_property_set_description(obj, "msel", 698 "Mode Select (MSEL[3:0]) pin state"); 699 700 s->serial = OTP_SERIAL; 701 object_property_add(obj, "serial", "uint32", 702 sifive_u_machine_get_uint32_prop, 703 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 704 object_property_set_description(obj, "serial", "Board serial number"); 705 } 706 707 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 708 { 709 MachineClass *mc = MACHINE_CLASS(oc); 710 711 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 712 mc->init = sifive_u_machine_init; 713 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 714 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 715 mc->default_cpu_type = SIFIVE_U_CPU; 716 mc->default_cpus = mc->min_cpus; 717 718 object_class_property_add_bool(oc, "start-in-flash", 719 sifive_u_machine_get_start_in_flash, 720 sifive_u_machine_set_start_in_flash); 721 object_class_property_set_description(oc, "start-in-flash", 722 "Set on to tell QEMU's ROM to jump to " 723 "flash. Otherwise QEMU will jump to DRAM " 724 "or L2LIM depending on the msel value"); 725 } 726 727 static const TypeInfo sifive_u_machine_typeinfo = { 728 .name = MACHINE_TYPE_NAME("sifive_u"), 729 .parent = TYPE_MACHINE, 730 .class_init = sifive_u_machine_class_init, 731 .instance_init = sifive_u_machine_instance_init, 732 .instance_size = sizeof(SiFiveUState), 733 }; 734 735 static void sifive_u_machine_init_register_types(void) 736 { 737 type_register_static(&sifive_u_machine_typeinfo); 738 } 739 740 type_init(sifive_u_machine_init_register_types) 741 742 static void sifive_u_soc_instance_init(Object *obj) 743 { 744 SiFiveUSoCState *s = RISCV_U_SOC(obj); 745 746 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 747 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 748 749 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 750 TYPE_RISCV_HART_ARRAY); 751 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 752 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 753 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 754 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 755 756 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 757 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 758 759 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 760 TYPE_RISCV_HART_ARRAY); 761 762 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 763 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 764 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 765 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 766 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 767 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); 768 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); 769 } 770 771 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 772 { 773 MachineState *ms = MACHINE(qdev_get_machine()); 774 SiFiveUSoCState *s = RISCV_U_SOC(dev); 775 const MemMapEntry *memmap = sifive_u_memmap; 776 MemoryRegion *system_memory = get_system_memory(); 777 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 778 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 779 char *plic_hart_config; 780 size_t plic_hart_config_len; 781 int i; 782 NICInfo *nd = &nd_table[0]; 783 784 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 785 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 786 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 787 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 788 789 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 790 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 791 /* 792 * The cluster must be realized after the RISC-V hart array container, 793 * as the container's CPU object is only created on realize, and the 794 * CPU must exist and have been parented into the cluster before the 795 * cluster is realized. 796 */ 797 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 798 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 799 800 /* boot rom */ 801 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 802 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 803 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 804 mask_rom); 805 806 /* 807 * Add L2-LIM at reset size. 808 * This should be reduced in size as the L2 Cache Controller WayEnable 809 * register is incremented. Unfortunately I don't see a nice (or any) way 810 * to handle reducing or blocking out the L2 LIM while still allowing it 811 * be re returned to all enabled after a reset. For the time being, just 812 * leave it enabled all the time. This won't break anything, but will be 813 * too generous to misbehaving guests. 814 */ 815 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 816 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 817 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 818 l2lim_mem); 819 820 /* create PLIC hart topology configuration string */ 821 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 822 ms->smp.cpus; 823 plic_hart_config = g_malloc0(plic_hart_config_len); 824 for (i = 0; i < ms->smp.cpus; i++) { 825 if (i != 0) { 826 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 827 plic_hart_config_len); 828 } else { 829 strncat(plic_hart_config, "M", plic_hart_config_len); 830 } 831 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 832 } 833 834 /* MMIO */ 835 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 836 plic_hart_config, 0, 837 SIFIVE_U_PLIC_NUM_SOURCES, 838 SIFIVE_U_PLIC_NUM_PRIORITIES, 839 SIFIVE_U_PLIC_PRIORITY_BASE, 840 SIFIVE_U_PLIC_PENDING_BASE, 841 SIFIVE_U_PLIC_ENABLE_BASE, 842 SIFIVE_U_PLIC_ENABLE_STRIDE, 843 SIFIVE_U_PLIC_CONTEXT_BASE, 844 SIFIVE_U_PLIC_CONTEXT_STRIDE, 845 memmap[SIFIVE_U_DEV_PLIC].size); 846 g_free(plic_hart_config); 847 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 848 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 849 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 850 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 851 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, 852 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, 853 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 854 CLINT_TIMEBASE_FREQ, false); 855 856 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 857 return; 858 } 859 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 860 861 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 862 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 863 return; 864 } 865 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 866 867 /* Pass all GPIOs to the SOC layer so they are available to the board */ 868 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 869 870 /* Connect GPIO interrupts to the PLIC */ 871 for (i = 0; i < 16; i++) { 872 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 873 qdev_get_gpio_in(DEVICE(s->plic), 874 SIFIVE_U_GPIO_IRQ0 + i)); 875 } 876 877 /* PDMA */ 878 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 879 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 880 881 /* Connect PDMA interrupts to the PLIC */ 882 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 883 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 884 qdev_get_gpio_in(DEVICE(s->plic), 885 SIFIVE_U_PDMA_IRQ0 + i)); 886 } 887 888 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 889 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 890 return; 891 } 892 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 893 894 /* FIXME use qdev NIC properties instead of nd_table[] */ 895 if (nd->used) { 896 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 897 qdev_set_nic_properties(DEVICE(&s->gem), nd); 898 } 899 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 900 &error_abort); 901 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 902 return; 903 } 904 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 905 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 906 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 907 908 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 909 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 910 911 create_unimplemented_device("riscv.sifive.u.dmc", 912 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 913 914 create_unimplemented_device("riscv.sifive.u.l2cc", 915 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 916 917 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); 918 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, 919 memmap[SIFIVE_U_DEV_QSPI0].base); 920 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, 921 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); 922 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); 923 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, 924 memmap[SIFIVE_U_DEV_QSPI2].base); 925 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, 926 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); 927 } 928 929 static Property sifive_u_soc_props[] = { 930 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 931 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 932 DEFINE_PROP_END_OF_LIST() 933 }; 934 935 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 936 { 937 DeviceClass *dc = DEVICE_CLASS(oc); 938 939 device_class_set_props(dc, sifive_u_soc_props); 940 dc->realize = sifive_u_soc_realize; 941 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 942 dc->user_creatable = false; 943 } 944 945 static const TypeInfo sifive_u_soc_type_info = { 946 .name = TYPE_RISCV_U_SOC, 947 .parent = TYPE_DEVICE, 948 .instance_size = sizeof(SiFiveUSoCState), 949 .instance_init = sifive_u_soc_instance_init, 950 .class_init = sifive_u_soc_class_init, 951 }; 952 953 static void sifive_u_soc_register_types(void) 954 { 955 type_register_static(&sifive_u_soc_type_info); 956 } 957 958 type_init(sifive_u_soc_register_types) 959