1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) OTP (One-Time Programmable) memory with stored serial number 15 * 5) GEM (Gigabit Ethernet Controller) and management block 16 * 17 * This board currently generates devicetree dynamically that indicates at least 18 * two harts and up to five harts. 19 * 20 * This program is free software; you can redistribute it and/or modify it 21 * under the terms and conditions of the GNU General Public License, 22 * version 2 or later, as published by the Free Software Foundation. 23 * 24 * This program is distributed in the hope it will be useful, but WITHOUT 25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 27 * more details. 28 * 29 * You should have received a copy of the GNU General Public License along with 30 * this program. If not, see <http://www.gnu.org/licenses/>. 31 */ 32 33 #include "qemu/osdep.h" 34 #include "qemu/log.h" 35 #include "qemu/error-report.h" 36 #include "qapi/error.h" 37 #include "qapi/visitor.h" 38 #include "hw/boards.h" 39 #include "hw/loader.h" 40 #include "hw/sysbus.h" 41 #include "hw/char/serial.h" 42 #include "hw/cpu/cluster.h" 43 #include "hw/misc/unimp.h" 44 #include "target/riscv/cpu.h" 45 #include "hw/riscv/riscv_hart.h" 46 #include "hw/riscv/sifive_plic.h" 47 #include "hw/riscv/sifive_clint.h" 48 #include "hw/riscv/sifive_uart.h" 49 #include "hw/riscv/sifive_u.h" 50 #include "hw/riscv/boot.h" 51 #include "chardev/char.h" 52 #include "net/eth.h" 53 #include "sysemu/arch_init.h" 54 #include "sysemu/device_tree.h" 55 #include "sysemu/sysemu.h" 56 #include "exec/address-spaces.h" 57 58 #include <libfdt.h> 59 60 #if defined(TARGET_RISCV32) 61 # define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin" 62 #else 63 # define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" 64 #endif 65 66 static const struct MemmapEntry { 67 hwaddr base; 68 hwaddr size; 69 } sifive_u_memmap[] = { 70 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 71 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 72 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 73 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, 74 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 75 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, 76 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, 77 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, 78 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, 79 [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, 80 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 81 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, 82 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, 83 }; 84 85 #define OTP_SERIAL 1 86 #define GEM_REVISION 0x10070109 87 88 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 89 uint64_t mem_size, const char *cmdline) 90 { 91 MachineState *ms = MACHINE(qdev_get_machine()); 92 void *fdt; 93 int cpu; 94 uint32_t *cells; 95 char *nodename; 96 char ethclk_names[] = "pclk\0hclk"; 97 uint32_t plic_phandle, prci_phandle, phandle = 1; 98 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 99 100 fdt = s->fdt = create_device_tree(&s->fdt_size); 101 if (!fdt) { 102 error_report("create_device_tree() failed"); 103 exit(1); 104 } 105 106 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 107 qemu_fdt_setprop_string(fdt, "/", "compatible", 108 "sifive,hifive-unleashed-a00"); 109 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 110 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 111 112 qemu_fdt_add_subnode(fdt, "/soc"); 113 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 114 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 115 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 116 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 117 118 hfclk_phandle = phandle++; 119 nodename = g_strdup_printf("/hfclk"); 120 qemu_fdt_add_subnode(fdt, nodename); 121 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 122 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 123 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 124 SIFIVE_U_HFCLK_FREQ); 125 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 126 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 127 g_free(nodename); 128 129 rtcclk_phandle = phandle++; 130 nodename = g_strdup_printf("/rtcclk"); 131 qemu_fdt_add_subnode(fdt, nodename); 132 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 133 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 134 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 135 SIFIVE_U_RTCCLK_FREQ); 136 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 137 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 138 g_free(nodename); 139 140 nodename = g_strdup_printf("/memory@%lx", 141 (long)memmap[SIFIVE_U_DRAM].base); 142 qemu_fdt_add_subnode(fdt, nodename); 143 qemu_fdt_setprop_cells(fdt, nodename, "reg", 144 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 145 mem_size >> 32, mem_size); 146 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 147 g_free(nodename); 148 149 qemu_fdt_add_subnode(fdt, "/cpus"); 150 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 151 SIFIVE_CLINT_TIMEBASE_FREQ); 152 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 153 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 154 155 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 156 int cpu_phandle = phandle++; 157 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 158 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 159 char *isa; 160 qemu_fdt_add_subnode(fdt, nodename); 161 /* cpu 0 is the management hart that does not have mmu */ 162 if (cpu != 0) { 163 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 164 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 165 } else { 166 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 167 } 168 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 169 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 170 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 171 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 172 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 173 qemu_fdt_add_subnode(fdt, intc); 174 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 175 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 176 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 177 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 178 g_free(isa); 179 g_free(intc); 180 g_free(nodename); 181 } 182 183 cells = g_new0(uint32_t, ms->smp.cpus * 4); 184 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 185 nodename = 186 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 187 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 188 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 189 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 190 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 191 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 192 g_free(nodename); 193 } 194 nodename = g_strdup_printf("/soc/clint@%lx", 195 (long)memmap[SIFIVE_U_CLINT].base); 196 qemu_fdt_add_subnode(fdt, nodename); 197 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 198 qemu_fdt_setprop_cells(fdt, nodename, "reg", 199 0x0, memmap[SIFIVE_U_CLINT].base, 200 0x0, memmap[SIFIVE_U_CLINT].size); 201 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 202 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 203 g_free(cells); 204 g_free(nodename); 205 206 prci_phandle = phandle++; 207 nodename = g_strdup_printf("/soc/clock-controller@%lx", 208 (long)memmap[SIFIVE_U_PRCI].base); 209 qemu_fdt_add_subnode(fdt, nodename); 210 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 211 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 212 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 213 hfclk_phandle, rtcclk_phandle); 214 qemu_fdt_setprop_cells(fdt, nodename, "reg", 215 0x0, memmap[SIFIVE_U_PRCI].base, 216 0x0, memmap[SIFIVE_U_PRCI].size); 217 qemu_fdt_setprop_string(fdt, nodename, "compatible", 218 "sifive,fu540-c000-prci"); 219 g_free(nodename); 220 221 plic_phandle = phandle++; 222 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 223 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 224 nodename = 225 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 226 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 227 /* cpu 0 is the management hart that does not have S-mode */ 228 if (cpu == 0) { 229 cells[0] = cpu_to_be32(intc_phandle); 230 cells[1] = cpu_to_be32(IRQ_M_EXT); 231 } else { 232 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 233 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 234 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 235 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 236 } 237 g_free(nodename); 238 } 239 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 240 (long)memmap[SIFIVE_U_PLIC].base); 241 qemu_fdt_add_subnode(fdt, nodename); 242 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 243 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 244 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 245 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 246 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 247 qemu_fdt_setprop_cells(fdt, nodename, "reg", 248 0x0, memmap[SIFIVE_U_PLIC].base, 249 0x0, memmap[SIFIVE_U_PLIC].size); 250 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 251 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 252 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 253 g_free(cells); 254 g_free(nodename); 255 256 phy_phandle = phandle++; 257 nodename = g_strdup_printf("/soc/ethernet@%lx", 258 (long)memmap[SIFIVE_U_GEM].base); 259 qemu_fdt_add_subnode(fdt, nodename); 260 qemu_fdt_setprop_string(fdt, nodename, "compatible", 261 "sifive,fu540-c000-gem"); 262 qemu_fdt_setprop_cells(fdt, nodename, "reg", 263 0x0, memmap[SIFIVE_U_GEM].base, 264 0x0, memmap[SIFIVE_U_GEM].size, 265 0x0, memmap[SIFIVE_U_GEM_MGMT].base, 266 0x0, memmap[SIFIVE_U_GEM_MGMT].size); 267 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 268 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 269 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 270 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 271 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 272 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 273 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 274 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 275 sizeof(ethclk_names)); 276 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 277 s->soc.gem.conf.macaddr.a, ETH_ALEN); 278 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 279 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 280 281 qemu_fdt_add_subnode(fdt, "/aliases"); 282 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 283 284 g_free(nodename); 285 286 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 287 (long)memmap[SIFIVE_U_GEM].base); 288 qemu_fdt_add_subnode(fdt, nodename); 289 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 290 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 291 g_free(nodename); 292 293 nodename = g_strdup_printf("/soc/serial@%lx", 294 (long)memmap[SIFIVE_U_UART0].base); 295 qemu_fdt_add_subnode(fdt, nodename); 296 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 297 qemu_fdt_setprop_cells(fdt, nodename, "reg", 298 0x0, memmap[SIFIVE_U_UART0].base, 299 0x0, memmap[SIFIVE_U_UART0].size); 300 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 301 prci_phandle, PRCI_CLK_TLCLK); 302 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 303 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 304 305 qemu_fdt_add_subnode(fdt, "/chosen"); 306 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 307 if (cmdline) { 308 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 309 } 310 311 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 312 313 g_free(nodename); 314 } 315 316 static void sifive_u_machine_init(MachineState *machine) 317 { 318 const struct MemmapEntry *memmap = sifive_u_memmap; 319 SiFiveUState *s = RISCV_U_MACHINE(machine); 320 MemoryRegion *system_memory = get_system_memory(); 321 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 322 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 323 target_ulong start_addr = memmap[SIFIVE_U_DRAM].base; 324 int i; 325 326 /* Initialize SoC */ 327 object_initialize_child(OBJECT(machine), "soc", &s->soc, 328 sizeof(s->soc), TYPE_RISCV_U_SOC, 329 &error_abort, NULL); 330 object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", 331 &error_abort); 332 object_property_set_bool(OBJECT(&s->soc), true, "realized", 333 &error_abort); 334 335 /* register RAM */ 336 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 337 machine->ram_size, &error_fatal); 338 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 339 main_mem); 340 341 /* register QSPI0 Flash */ 342 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 343 memmap[SIFIVE_U_FLASH0].size, &error_fatal); 344 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base, 345 flash0); 346 347 /* create device tree */ 348 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 349 350 riscv_find_and_load_firmware(machine, BIOS_FILENAME, 351 memmap[SIFIVE_U_DRAM].base); 352 353 if (machine->kernel_filename) { 354 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename, 355 NULL); 356 357 if (machine->initrd_filename) { 358 hwaddr start; 359 hwaddr end = riscv_load_initrd(machine->initrd_filename, 360 machine->ram_size, kernel_entry, 361 &start); 362 qemu_fdt_setprop_cell(s->fdt, "/chosen", 363 "linux,initrd-start", start); 364 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 365 end); 366 } 367 } 368 369 if (s->start_in_flash) { 370 start_addr = memmap[SIFIVE_U_FLASH0].base; 371 } 372 373 /* reset vector */ 374 uint32_t reset_vec[8] = { 375 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 376 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 377 0xf1402573, /* csrr a0, mhartid */ 378 #if defined(TARGET_RISCV32) 379 0x0182a283, /* lw t0, 24(t0) */ 380 #elif defined(TARGET_RISCV64) 381 0x0182b283, /* ld t0, 24(t0) */ 382 #endif 383 0x00028067, /* jr t0 */ 384 0x00000000, 385 start_addr, /* start: .dword */ 386 0x00000000, 387 /* dtb: */ 388 }; 389 390 /* copy in the reset vector in little_endian byte order */ 391 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 392 reset_vec[i] = cpu_to_le32(reset_vec[i]); 393 } 394 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 395 memmap[SIFIVE_U_MROM].base, &address_space_memory); 396 397 /* copy in the device tree */ 398 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 399 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 400 error_report("not enough space to store device-tree"); 401 exit(1); 402 } 403 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 404 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 405 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 406 &address_space_memory); 407 } 408 409 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 410 { 411 SiFiveUState *s = RISCV_U_MACHINE(obj); 412 413 return s->start_in_flash; 414 } 415 416 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 417 { 418 SiFiveUState *s = RISCV_U_MACHINE(obj); 419 420 s->start_in_flash = value; 421 } 422 423 static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name, 424 void *opaque, Error **errp) 425 { 426 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 427 } 428 429 static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name, 430 void *opaque, Error **errp) 431 { 432 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 433 } 434 435 static void sifive_u_machine_instance_init(Object *obj) 436 { 437 SiFiveUState *s = RISCV_U_MACHINE(obj); 438 439 s->start_in_flash = false; 440 object_property_add_bool(obj, "start-in-flash", sifive_u_machine_get_start_in_flash, 441 sifive_u_machine_set_start_in_flash, NULL); 442 object_property_set_description(obj, "start-in-flash", 443 "Set on to tell QEMU's ROM to jump to " 444 "flash. Otherwise QEMU will jump to DRAM", 445 NULL); 446 447 s->serial = OTP_SERIAL; 448 object_property_add(obj, "serial", "uint32", sifive_u_machine_get_serial, 449 sifive_u_machine_set_serial, NULL, &s->serial, NULL); 450 object_property_set_description(obj, "serial", "Board serial number", NULL); 451 } 452 453 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 454 { 455 MachineClass *mc = MACHINE_CLASS(oc); 456 457 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 458 mc->init = sifive_u_machine_init; 459 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 460 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 461 mc->default_cpus = mc->min_cpus; 462 } 463 464 static const TypeInfo sifive_u_machine_typeinfo = { 465 .name = MACHINE_TYPE_NAME("sifive_u"), 466 .parent = TYPE_MACHINE, 467 .class_init = sifive_u_machine_class_init, 468 .instance_init = sifive_u_machine_instance_init, 469 .instance_size = sizeof(SiFiveUState), 470 }; 471 472 static void sifive_u_machine_init_register_types(void) 473 { 474 type_register_static(&sifive_u_machine_typeinfo); 475 } 476 477 type_init(sifive_u_machine_init_register_types) 478 479 static void riscv_sifive_u_soc_init(Object *obj) 480 { 481 MachineState *ms = MACHINE(qdev_get_machine()); 482 SiFiveUSoCState *s = RISCV_U_SOC(obj); 483 484 object_initialize_child(obj, "e-cluster", &s->e_cluster, 485 sizeof(s->e_cluster), TYPE_CPU_CLUSTER, 486 &error_abort, NULL); 487 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 488 489 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", 490 &s->e_cpus, sizeof(s->e_cpus), 491 TYPE_RISCV_HART_ARRAY, &error_abort, 492 NULL); 493 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 494 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 495 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 496 497 object_initialize_child(obj, "u-cluster", &s->u_cluster, 498 sizeof(s->u_cluster), TYPE_CPU_CLUSTER, 499 &error_abort, NULL); 500 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 501 502 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", 503 &s->u_cpus, sizeof(s->u_cpus), 504 TYPE_RISCV_HART_ARRAY, &error_abort, 505 NULL); 506 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 507 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 508 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); 509 510 sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), 511 TYPE_SIFIVE_U_PRCI); 512 sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), 513 TYPE_SIFIVE_U_OTP); 514 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), 515 TYPE_CADENCE_GEM); 516 } 517 518 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 519 { 520 MachineState *ms = MACHINE(qdev_get_machine()); 521 SiFiveUSoCState *s = RISCV_U_SOC(dev); 522 const struct MemmapEntry *memmap = sifive_u_memmap; 523 MemoryRegion *system_memory = get_system_memory(); 524 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 525 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 526 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; 527 char *plic_hart_config; 528 size_t plic_hart_config_len; 529 int i; 530 Error *err = NULL; 531 NICInfo *nd = &nd_table[0]; 532 533 object_property_set_bool(OBJECT(&s->e_cpus), true, "realized", 534 &error_abort); 535 object_property_set_bool(OBJECT(&s->u_cpus), true, "realized", 536 &error_abort); 537 /* 538 * The cluster must be realized after the RISC-V hart array container, 539 * as the container's CPU object is only created on realize, and the 540 * CPU must exist and have been parented into the cluster before the 541 * cluster is realized. 542 */ 543 object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", 544 &error_abort); 545 object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", 546 &error_abort); 547 548 /* boot rom */ 549 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 550 memmap[SIFIVE_U_MROM].size, &error_fatal); 551 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 552 mask_rom); 553 554 /* 555 * Add L2-LIM at reset size. 556 * This should be reduced in size as the L2 Cache Controller WayEnable 557 * register is incremented. Unfortunately I don't see a nice (or any) way 558 * to handle reducing or blocking out the L2 LIM while still allowing it 559 * be re returned to all enabled after a reset. For the time being, just 560 * leave it enabled all the time. This won't break anything, but will be 561 * too generous to misbehaving guests. 562 */ 563 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 564 memmap[SIFIVE_U_L2LIM].size, &error_fatal); 565 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, 566 l2lim_mem); 567 568 /* create PLIC hart topology configuration string */ 569 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 570 ms->smp.cpus; 571 plic_hart_config = g_malloc0(plic_hart_config_len); 572 for (i = 0; i < ms->smp.cpus; i++) { 573 if (i != 0) { 574 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 575 plic_hart_config_len); 576 } else { 577 strncat(plic_hart_config, "M", plic_hart_config_len); 578 } 579 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 580 } 581 582 /* MMIO */ 583 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 584 plic_hart_config, 585 SIFIVE_U_PLIC_NUM_SOURCES, 586 SIFIVE_U_PLIC_NUM_PRIORITIES, 587 SIFIVE_U_PLIC_PRIORITY_BASE, 588 SIFIVE_U_PLIC_PENDING_BASE, 589 SIFIVE_U_PLIC_ENABLE_BASE, 590 SIFIVE_U_PLIC_ENABLE_STRIDE, 591 SIFIVE_U_PLIC_CONTEXT_BASE, 592 SIFIVE_U_PLIC_CONTEXT_STRIDE, 593 memmap[SIFIVE_U_PLIC].size); 594 g_free(plic_hart_config); 595 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 596 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 597 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 598 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 599 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 600 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 601 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); 602 603 object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); 604 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); 605 606 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 607 object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); 608 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); 609 610 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { 611 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); 612 } 613 614 if (nd->used) { 615 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 616 qdev_set_nic_properties(DEVICE(&s->gem), nd); 617 } 618 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 619 &error_abort); 620 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); 621 if (err) { 622 error_propagate(errp, err); 623 return; 624 } 625 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 626 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 627 plic_gpios[SIFIVE_U_GEM_IRQ]); 628 629 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 630 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); 631 } 632 633 static Property riscv_sifive_u_soc_props[] = { 634 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 635 DEFINE_PROP_END_OF_LIST() 636 }; 637 638 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 639 { 640 DeviceClass *dc = DEVICE_CLASS(oc); 641 642 device_class_set_props(dc, riscv_sifive_u_soc_props); 643 dc->realize = riscv_sifive_u_soc_realize; 644 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 645 dc->user_creatable = false; 646 } 647 648 static const TypeInfo riscv_sifive_u_soc_type_info = { 649 .name = TYPE_RISCV_U_SOC, 650 .parent = TYPE_DEVICE, 651 .instance_size = sizeof(SiFiveUSoCState), 652 .instance_init = riscv_sifive_u_soc_init, 653 .class_init = riscv_sifive_u_soc_class_init, 654 }; 655 656 static void riscv_sifive_u_soc_register_types(void) 657 { 658 type_register_static(&riscv_sifive_u_soc_type_info); 659 } 660 661 type_init(riscv_sifive_u_soc_register_types) 662