1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 19 * This board currently generates devicetree dynamically that indicates at least 20 * two harts and up to five harts. 21 * 22 * This program is free software; you can redistribute it and/or modify it 23 * under the terms and conditions of the GNU General Public License, 24 * version 2 or later, as published by the Free Software Foundation. 25 * 26 * This program is distributed in the hope it will be useful, but WITHOUT 27 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 28 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 29 * more details. 30 * 31 * You should have received a copy of the GNU General Public License along with 32 * this program. If not, see <http://www.gnu.org/licenses/>. 33 */ 34 35 #include "qemu/osdep.h" 36 #include "qemu/log.h" 37 #include "qemu/error-report.h" 38 #include "qapi/error.h" 39 #include "qapi/visitor.h" 40 #include "hw/boards.h" 41 #include "hw/irq.h" 42 #include "hw/loader.h" 43 #include "hw/sysbus.h" 44 #include "hw/char/serial.h" 45 #include "hw/cpu/cluster.h" 46 #include "hw/misc/unimp.h" 47 #include "target/riscv/cpu.h" 48 #include "hw/riscv/riscv_hart.h" 49 #include "hw/riscv/sifive_u.h" 50 #include "hw/riscv/boot.h" 51 #include "hw/char/sifive_uart.h" 52 #include "hw/intc/sifive_clint.h" 53 #include "hw/intc/sifive_plic.h" 54 #include "chardev/char.h" 55 #include "net/eth.h" 56 #include "sysemu/arch_init.h" 57 #include "sysemu/device_tree.h" 58 #include "sysemu/runstate.h" 59 #include "sysemu/sysemu.h" 60 61 #include <libfdt.h> 62 63 #if defined(TARGET_RISCV32) 64 # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" 65 #else 66 # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" 67 #endif 68 69 static const struct MemmapEntry { 70 hwaddr base; 71 hwaddr size; 72 } sifive_u_memmap[] = { 73 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 74 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 75 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 76 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 77 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 78 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 79 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 80 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 81 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 82 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 83 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 84 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 85 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 86 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 87 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 88 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 89 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 90 }; 91 92 #define OTP_SERIAL 1 93 #define GEM_REVISION 0x10070109 94 95 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 96 uint64_t mem_size, const char *cmdline) 97 { 98 MachineState *ms = MACHINE(qdev_get_machine()); 99 void *fdt; 100 int cpu; 101 uint32_t *cells; 102 char *nodename; 103 const char *dtb_filename; 104 char ethclk_names[] = "pclk\0hclk"; 105 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 106 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 107 108 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 109 if (dtb_filename) { 110 fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size); 111 if (!fdt) { 112 error_report("load_device_tree() failed"); 113 exit(1); 114 } 115 goto update_bootargs; 116 } else { 117 fdt = s->fdt = create_device_tree(&s->fdt_size); 118 if (!fdt) { 119 error_report("create_device_tree() failed"); 120 exit(1); 121 } 122 } 123 124 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 125 qemu_fdt_setprop_string(fdt, "/", "compatible", 126 "sifive,hifive-unleashed-a00"); 127 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 128 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 129 130 qemu_fdt_add_subnode(fdt, "/soc"); 131 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 132 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 133 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 134 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 135 136 hfclk_phandle = phandle++; 137 nodename = g_strdup_printf("/hfclk"); 138 qemu_fdt_add_subnode(fdt, nodename); 139 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 140 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 141 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 142 SIFIVE_U_HFCLK_FREQ); 143 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 144 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 145 g_free(nodename); 146 147 rtcclk_phandle = phandle++; 148 nodename = g_strdup_printf("/rtcclk"); 149 qemu_fdt_add_subnode(fdt, nodename); 150 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 151 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 152 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 153 SIFIVE_U_RTCCLK_FREQ); 154 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 155 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 156 g_free(nodename); 157 158 nodename = g_strdup_printf("/memory@%lx", 159 (long)memmap[SIFIVE_U_DEV_DRAM].base); 160 qemu_fdt_add_subnode(fdt, nodename); 161 qemu_fdt_setprop_cells(fdt, nodename, "reg", 162 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 163 mem_size >> 32, mem_size); 164 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 165 g_free(nodename); 166 167 qemu_fdt_add_subnode(fdt, "/cpus"); 168 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 169 SIFIVE_CLINT_TIMEBASE_FREQ); 170 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 171 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 172 173 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 174 int cpu_phandle = phandle++; 175 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 176 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 177 char *isa; 178 qemu_fdt_add_subnode(fdt, nodename); 179 /* cpu 0 is the management hart that does not have mmu */ 180 if (cpu != 0) { 181 #if defined(TARGET_RISCV32) 182 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 183 #else 184 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 185 #endif 186 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 187 } else { 188 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 189 } 190 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 191 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 192 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 193 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 194 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 195 qemu_fdt_add_subnode(fdt, intc); 196 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 197 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 198 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 199 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 200 g_free(isa); 201 g_free(intc); 202 g_free(nodename); 203 } 204 205 cells = g_new0(uint32_t, ms->smp.cpus * 4); 206 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 207 nodename = 208 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 209 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 210 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 211 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 212 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 213 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 214 g_free(nodename); 215 } 216 nodename = g_strdup_printf("/soc/clint@%lx", 217 (long)memmap[SIFIVE_U_DEV_CLINT].base); 218 qemu_fdt_add_subnode(fdt, nodename); 219 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 220 qemu_fdt_setprop_cells(fdt, nodename, "reg", 221 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 222 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 223 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 224 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 225 g_free(cells); 226 g_free(nodename); 227 228 nodename = g_strdup_printf("/soc/otp@%lx", 229 (long)memmap[SIFIVE_U_DEV_OTP].base); 230 qemu_fdt_add_subnode(fdt, nodename); 231 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 232 qemu_fdt_setprop_cells(fdt, nodename, "reg", 233 0x0, memmap[SIFIVE_U_DEV_OTP].base, 234 0x0, memmap[SIFIVE_U_DEV_OTP].size); 235 qemu_fdt_setprop_string(fdt, nodename, "compatible", 236 "sifive,fu540-c000-otp"); 237 g_free(nodename); 238 239 prci_phandle = phandle++; 240 nodename = g_strdup_printf("/soc/clock-controller@%lx", 241 (long)memmap[SIFIVE_U_DEV_PRCI].base); 242 qemu_fdt_add_subnode(fdt, nodename); 243 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 244 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 245 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 246 hfclk_phandle, rtcclk_phandle); 247 qemu_fdt_setprop_cells(fdt, nodename, "reg", 248 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 249 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 250 qemu_fdt_setprop_string(fdt, nodename, "compatible", 251 "sifive,fu540-c000-prci"); 252 g_free(nodename); 253 254 plic_phandle = phandle++; 255 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 256 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 257 nodename = 258 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 259 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 260 /* cpu 0 is the management hart that does not have S-mode */ 261 if (cpu == 0) { 262 cells[0] = cpu_to_be32(intc_phandle); 263 cells[1] = cpu_to_be32(IRQ_M_EXT); 264 } else { 265 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 266 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 267 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 268 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 269 } 270 g_free(nodename); 271 } 272 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 273 (long)memmap[SIFIVE_U_DEV_PLIC].base); 274 qemu_fdt_add_subnode(fdt, nodename); 275 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 276 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 277 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 278 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 279 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 280 qemu_fdt_setprop_cells(fdt, nodename, "reg", 281 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 282 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 283 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 284 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 285 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 286 g_free(cells); 287 g_free(nodename); 288 289 gpio_phandle = phandle++; 290 nodename = g_strdup_printf("/soc/gpio@%lx", 291 (long)memmap[SIFIVE_U_DEV_GPIO].base); 292 qemu_fdt_add_subnode(fdt, nodename); 293 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 294 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 295 prci_phandle, PRCI_CLK_TLCLK); 296 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 297 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 298 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 299 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 300 qemu_fdt_setprop_cells(fdt, nodename, "reg", 301 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 302 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 303 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 304 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 305 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 306 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 307 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 308 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 309 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 310 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 311 g_free(nodename); 312 313 nodename = g_strdup_printf("/gpio-restart"); 314 qemu_fdt_add_subnode(fdt, nodename); 315 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 316 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 317 g_free(nodename); 318 319 nodename = g_strdup_printf("/soc/dma@%lx", 320 (long)memmap[SIFIVE_U_DEV_PDMA].base); 321 qemu_fdt_add_subnode(fdt, nodename); 322 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 323 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 324 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 325 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 326 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 327 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 328 qemu_fdt_setprop_cells(fdt, nodename, "reg", 329 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 330 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 331 qemu_fdt_setprop_string(fdt, nodename, "compatible", 332 "sifive,fu540-c000-pdma"); 333 g_free(nodename); 334 335 nodename = g_strdup_printf("/soc/cache-controller@%lx", 336 (long)memmap[SIFIVE_U_DEV_L2CC].base); 337 qemu_fdt_add_subnode(fdt, nodename); 338 qemu_fdt_setprop_cells(fdt, nodename, "reg", 339 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 340 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 341 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 342 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 343 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 344 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 345 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 346 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 347 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 348 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 349 qemu_fdt_setprop_string(fdt, nodename, "compatible", 350 "sifive,fu540-c000-ccache"); 351 g_free(nodename); 352 353 phy_phandle = phandle++; 354 nodename = g_strdup_printf("/soc/ethernet@%lx", 355 (long)memmap[SIFIVE_U_DEV_GEM].base); 356 qemu_fdt_add_subnode(fdt, nodename); 357 qemu_fdt_setprop_string(fdt, nodename, "compatible", 358 "sifive,fu540-c000-gem"); 359 qemu_fdt_setprop_cells(fdt, nodename, "reg", 360 0x0, memmap[SIFIVE_U_DEV_GEM].base, 361 0x0, memmap[SIFIVE_U_DEV_GEM].size, 362 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 363 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 364 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 365 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 366 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 367 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 368 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 369 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 370 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 371 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 372 sizeof(ethclk_names)); 373 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 374 s->soc.gem.conf.macaddr.a, ETH_ALEN); 375 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 376 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 377 378 qemu_fdt_add_subnode(fdt, "/aliases"); 379 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 380 381 g_free(nodename); 382 383 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 384 (long)memmap[SIFIVE_U_DEV_GEM].base); 385 qemu_fdt_add_subnode(fdt, nodename); 386 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 387 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 388 g_free(nodename); 389 390 nodename = g_strdup_printf("/soc/serial@%lx", 391 (long)memmap[SIFIVE_U_DEV_UART0].base); 392 qemu_fdt_add_subnode(fdt, nodename); 393 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 394 qemu_fdt_setprop_cells(fdt, nodename, "reg", 395 0x0, memmap[SIFIVE_U_DEV_UART0].base, 396 0x0, memmap[SIFIVE_U_DEV_UART0].size); 397 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 398 prci_phandle, PRCI_CLK_TLCLK); 399 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 400 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 401 402 qemu_fdt_add_subnode(fdt, "/chosen"); 403 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 404 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 405 406 g_free(nodename); 407 408 update_bootargs: 409 if (cmdline) { 410 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 411 } 412 } 413 414 static void sifive_u_machine_reset(void *opaque, int n, int level) 415 { 416 /* gpio pin active low triggers reset */ 417 if (!level) { 418 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 419 } 420 } 421 422 static void sifive_u_machine_init(MachineState *machine) 423 { 424 const struct MemmapEntry *memmap = sifive_u_memmap; 425 SiFiveUState *s = RISCV_U_MACHINE(machine); 426 MemoryRegion *system_memory = get_system_memory(); 427 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 428 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 429 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 430 target_ulong firmware_end_addr, kernel_start_addr; 431 uint32_t start_addr_hi32 = 0x00000000; 432 int i; 433 uint32_t fdt_load_addr; 434 uint64_t kernel_entry; 435 436 /* Initialize SoC */ 437 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 438 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 439 &error_abort); 440 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 441 &error_abort); 442 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 443 444 /* register RAM */ 445 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 446 machine->ram_size, &error_fatal); 447 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 448 main_mem); 449 450 /* register QSPI0 Flash */ 451 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 452 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 453 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 454 flash0); 455 456 /* register gpio-restart */ 457 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 458 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 459 460 /* create device tree */ 461 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 462 463 if (s->start_in_flash) { 464 /* 465 * If start_in_flash property is given, assign s->msel to a value 466 * that representing booting from QSPI0 memory-mapped flash. 467 * 468 * This also means that when both start_in_flash and msel properties 469 * are given, start_in_flash takes the precedence over msel. 470 * 471 * Note this is to keep backward compatibility not to break existing 472 * users that use start_in_flash property. 473 */ 474 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 475 } 476 477 switch (s->msel) { 478 case MSEL_MEMMAP_QSPI0_FLASH: 479 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 480 break; 481 case MSEL_L2LIM_QSPI0_FLASH: 482 case MSEL_L2LIM_QSPI2_SD: 483 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 484 break; 485 default: 486 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 487 break; 488 } 489 490 firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, 491 start_addr, NULL); 492 493 if (machine->kernel_filename) { 494 kernel_start_addr = riscv_calc_kernel_start_addr(machine, 495 firmware_end_addr); 496 497 kernel_entry = riscv_load_kernel(machine->kernel_filename, 498 kernel_start_addr, NULL); 499 500 if (machine->initrd_filename) { 501 hwaddr start; 502 hwaddr end = riscv_load_initrd(machine->initrd_filename, 503 machine->ram_size, kernel_entry, 504 &start); 505 qemu_fdt_setprop_cell(s->fdt, "/chosen", 506 "linux,initrd-start", start); 507 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 508 end); 509 } 510 } else { 511 /* 512 * If dynamic firmware is used, it doesn't know where is the next mode 513 * if kernel argument is not set. 514 */ 515 kernel_entry = 0; 516 } 517 518 /* Compute the fdt load address in dram */ 519 fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, 520 machine->ram_size, s->fdt); 521 #if defined(TARGET_RISCV64) 522 start_addr_hi32 = start_addr >> 32; 523 #endif 524 525 /* reset vector */ 526 uint32_t reset_vec[11] = { 527 s->msel, /* MSEL pin state */ 528 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 529 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 530 0xf1402573, /* csrr a0, mhartid */ 531 #if defined(TARGET_RISCV32) 532 0x0202a583, /* lw a1, 32(t0) */ 533 0x0182a283, /* lw t0, 24(t0) */ 534 #elif defined(TARGET_RISCV64) 535 0x0202b583, /* ld a1, 32(t0) */ 536 0x0182b283, /* ld t0, 24(t0) */ 537 #endif 538 0x00028067, /* jr t0 */ 539 start_addr, /* start: .dword */ 540 start_addr_hi32, 541 fdt_load_addr, /* fdt_laddr: .dword */ 542 0x00000000, 543 /* fw_dyn: */ 544 }; 545 546 /* copy in the reset vector in little_endian byte order */ 547 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 548 reset_vec[i] = cpu_to_le32(reset_vec[i]); 549 } 550 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 551 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 552 553 riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base, 554 memmap[SIFIVE_U_DEV_MROM].size, 555 sizeof(reset_vec), kernel_entry); 556 } 557 558 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 559 { 560 SiFiveUState *s = RISCV_U_MACHINE(obj); 561 562 return s->start_in_flash; 563 } 564 565 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 566 { 567 SiFiveUState *s = RISCV_U_MACHINE(obj); 568 569 s->start_in_flash = value; 570 } 571 572 static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, 573 const char *name, void *opaque, 574 Error **errp) 575 { 576 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 577 } 578 579 static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, 580 const char *name, void *opaque, 581 Error **errp) 582 { 583 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 584 } 585 586 static void sifive_u_machine_instance_init(Object *obj) 587 { 588 SiFiveUState *s = RISCV_U_MACHINE(obj); 589 590 s->start_in_flash = false; 591 s->msel = 0; 592 object_property_add(obj, "msel", "uint32", 593 sifive_u_machine_get_uint32_prop, 594 sifive_u_machine_set_uint32_prop, NULL, &s->msel); 595 object_property_set_description(obj, "msel", 596 "Mode Select (MSEL[3:0]) pin state"); 597 598 s->serial = OTP_SERIAL; 599 object_property_add(obj, "serial", "uint32", 600 sifive_u_machine_get_uint32_prop, 601 sifive_u_machine_set_uint32_prop, NULL, &s->serial); 602 object_property_set_description(obj, "serial", "Board serial number"); 603 } 604 605 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 606 { 607 MachineClass *mc = MACHINE_CLASS(oc); 608 609 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 610 mc->init = sifive_u_machine_init; 611 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 612 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 613 #if defined(TARGET_RISCV32) 614 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; 615 #elif defined(TARGET_RISCV64) 616 mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; 617 #endif 618 mc->default_cpus = mc->min_cpus; 619 620 object_class_property_add_bool(oc, "start-in-flash", 621 sifive_u_machine_get_start_in_flash, 622 sifive_u_machine_set_start_in_flash); 623 object_class_property_set_description(oc, "start-in-flash", 624 "Set on to tell QEMU's ROM to jump to " 625 "flash. Otherwise QEMU will jump to DRAM " 626 "or L2LIM depending on the msel value"); 627 } 628 629 static const TypeInfo sifive_u_machine_typeinfo = { 630 .name = MACHINE_TYPE_NAME("sifive_u"), 631 .parent = TYPE_MACHINE, 632 .class_init = sifive_u_machine_class_init, 633 .instance_init = sifive_u_machine_instance_init, 634 .instance_size = sizeof(SiFiveUState), 635 }; 636 637 static void sifive_u_machine_init_register_types(void) 638 { 639 type_register_static(&sifive_u_machine_typeinfo); 640 } 641 642 type_init(sifive_u_machine_init_register_types) 643 644 static void sifive_u_soc_instance_init(Object *obj) 645 { 646 SiFiveUSoCState *s = RISCV_U_SOC(obj); 647 648 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 649 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 650 651 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 652 TYPE_RISCV_HART_ARRAY); 653 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 654 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 655 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 656 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 657 658 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 659 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 660 661 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 662 TYPE_RISCV_HART_ARRAY); 663 664 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 665 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 666 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 667 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 668 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 669 } 670 671 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 672 { 673 MachineState *ms = MACHINE(qdev_get_machine()); 674 SiFiveUSoCState *s = RISCV_U_SOC(dev); 675 const struct MemmapEntry *memmap = sifive_u_memmap; 676 MemoryRegion *system_memory = get_system_memory(); 677 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 678 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 679 char *plic_hart_config; 680 size_t plic_hart_config_len; 681 int i; 682 NICInfo *nd = &nd_table[0]; 683 684 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 685 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 686 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 687 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 688 689 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 690 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 691 /* 692 * The cluster must be realized after the RISC-V hart array container, 693 * as the container's CPU object is only created on realize, and the 694 * CPU must exist and have been parented into the cluster before the 695 * cluster is realized. 696 */ 697 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 698 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 699 700 /* boot rom */ 701 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 702 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 703 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 704 mask_rom); 705 706 /* 707 * Add L2-LIM at reset size. 708 * This should be reduced in size as the L2 Cache Controller WayEnable 709 * register is incremented. Unfortunately I don't see a nice (or any) way 710 * to handle reducing or blocking out the L2 LIM while still allowing it 711 * be re returned to all enabled after a reset. For the time being, just 712 * leave it enabled all the time. This won't break anything, but will be 713 * too generous to misbehaving guests. 714 */ 715 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 716 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 717 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 718 l2lim_mem); 719 720 /* create PLIC hart topology configuration string */ 721 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 722 ms->smp.cpus; 723 plic_hart_config = g_malloc0(plic_hart_config_len); 724 for (i = 0; i < ms->smp.cpus; i++) { 725 if (i != 0) { 726 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 727 plic_hart_config_len); 728 } else { 729 strncat(plic_hart_config, "M", plic_hart_config_len); 730 } 731 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 732 } 733 734 /* MMIO */ 735 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 736 plic_hart_config, 0, 737 SIFIVE_U_PLIC_NUM_SOURCES, 738 SIFIVE_U_PLIC_NUM_PRIORITIES, 739 SIFIVE_U_PLIC_PRIORITY_BASE, 740 SIFIVE_U_PLIC_PENDING_BASE, 741 SIFIVE_U_PLIC_ENABLE_BASE, 742 SIFIVE_U_PLIC_ENABLE_STRIDE, 743 SIFIVE_U_PLIC_CONTEXT_BASE, 744 SIFIVE_U_PLIC_CONTEXT_STRIDE, 745 memmap[SIFIVE_U_DEV_PLIC].size); 746 g_free(plic_hart_config); 747 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 748 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 749 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 750 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 751 sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, 752 memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, 753 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 754 SIFIVE_CLINT_TIMEBASE_FREQ, false); 755 756 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 757 return; 758 } 759 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 760 761 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 762 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 763 return; 764 } 765 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 766 767 /* Pass all GPIOs to the SOC layer so they are available to the board */ 768 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 769 770 /* Connect GPIO interrupts to the PLIC */ 771 for (i = 0; i < 16; i++) { 772 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 773 qdev_get_gpio_in(DEVICE(s->plic), 774 SIFIVE_U_GPIO_IRQ0 + i)); 775 } 776 777 /* PDMA */ 778 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 779 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 780 781 /* Connect PDMA interrupts to the PLIC */ 782 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 783 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 784 qdev_get_gpio_in(DEVICE(s->plic), 785 SIFIVE_U_PDMA_IRQ0 + i)); 786 } 787 788 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 789 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 790 return; 791 } 792 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 793 794 /* FIXME use qdev NIC properties instead of nd_table[] */ 795 if (nd->used) { 796 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 797 qdev_set_nic_properties(DEVICE(&s->gem), nd); 798 } 799 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 800 &error_abort); 801 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 802 return; 803 } 804 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 805 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 806 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 807 808 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 809 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 810 811 create_unimplemented_device("riscv.sifive.u.dmc", 812 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 813 814 create_unimplemented_device("riscv.sifive.u.l2cc", 815 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 816 } 817 818 static Property sifive_u_soc_props[] = { 819 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 820 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 821 DEFINE_PROP_END_OF_LIST() 822 }; 823 824 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 825 { 826 DeviceClass *dc = DEVICE_CLASS(oc); 827 828 device_class_set_props(dc, sifive_u_soc_props); 829 dc->realize = sifive_u_soc_realize; 830 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 831 dc->user_creatable = false; 832 } 833 834 static const TypeInfo sifive_u_soc_type_info = { 835 .name = TYPE_RISCV_U_SOC, 836 .parent = TYPE_DEVICE, 837 .instance_size = sizeof(SiFiveUSoCState), 838 .instance_init = sifive_u_soc_instance_init, 839 .class_init = sifive_u_soc_class_init, 840 }; 841 842 static void sifive_u_soc_register_types(void) 843 { 844 type_register_static(&sifive_u_soc_type_info); 845 } 846 847 type_init(sifive_u_soc_register_types) 848