1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * 7 * Provides a board compatible with the SiFive Freedom U SDK: 8 * 9 * 0) UART 10 * 1) CLINT (Core Level Interruptor) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This board currently uses a hardcoded devicetree that indicates one hart. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms and conditions of the GNU General Public License, 17 * version 2 or later, as published by the Free Software Foundation. 18 * 19 * This program is distributed in the hope it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 22 * more details. 23 * 24 * You should have received a copy of the GNU General Public License along with 25 * this program. If not, see <http://www.gnu.org/licenses/>. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "qapi/error.h" 32 #include "hw/boards.h" 33 #include "hw/loader.h" 34 #include "hw/sysbus.h" 35 #include "hw/char/serial.h" 36 #include "target/riscv/cpu.h" 37 #include "hw/riscv/riscv_hart.h" 38 #include "hw/riscv/sifive_plic.h" 39 #include "hw/riscv/sifive_clint.h" 40 #include "hw/riscv/sifive_uart.h" 41 #include "hw/riscv/sifive_prci.h" 42 #include "hw/riscv/sifive_u.h" 43 #include "hw/riscv/boot.h" 44 #include "chardev/char.h" 45 #include "sysemu/arch_init.h" 46 #include "sysemu/device_tree.h" 47 #include "sysemu/sysemu.h" 48 #include "exec/address-spaces.h" 49 50 #include <libfdt.h> 51 52 #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" 53 54 static const struct MemmapEntry { 55 hwaddr base; 56 hwaddr size; 57 } sifive_u_memmap[] = { 58 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 59 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 60 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 61 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 62 [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, 63 [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, 64 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 65 [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, 66 }; 67 68 #define GEM_REVISION 0x10070109 69 70 static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 71 uint64_t mem_size, const char *cmdline) 72 { 73 void *fdt; 74 int cpu; 75 uint32_t *cells; 76 char *nodename; 77 char ethclk_names[] = "pclk\0hclk\0tx_clk"; 78 uint32_t plic_phandle, ethclk_phandle, phandle = 1; 79 uint32_t uartclk_phandle; 80 81 fdt = s->fdt = create_device_tree(&s->fdt_size); 82 if (!fdt) { 83 error_report("create_device_tree() failed"); 84 exit(1); 85 } 86 87 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 88 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 89 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 90 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 91 92 qemu_fdt_add_subnode(fdt, "/soc"); 93 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 94 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 95 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 96 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 97 98 nodename = g_strdup_printf("/memory@%lx", 99 (long)memmap[SIFIVE_U_DRAM].base); 100 qemu_fdt_add_subnode(fdt, nodename); 101 qemu_fdt_setprop_cells(fdt, nodename, "reg", 102 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 103 mem_size >> 32, mem_size); 104 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 105 g_free(nodename); 106 107 qemu_fdt_add_subnode(fdt, "/cpus"); 108 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 109 SIFIVE_CLINT_TIMEBASE_FREQ); 110 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 111 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 112 113 for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { 114 int cpu_phandle = phandle++; 115 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 116 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 117 char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); 118 qemu_fdt_add_subnode(fdt, nodename); 119 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 120 SIFIVE_U_CLOCK_FREQ); 121 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 122 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 123 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 124 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 125 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 126 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 127 qemu_fdt_add_subnode(fdt, intc); 128 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 129 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); 130 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 131 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 132 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 133 g_free(isa); 134 g_free(intc); 135 g_free(nodename); 136 } 137 138 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 139 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 140 nodename = 141 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 142 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 143 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 144 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 145 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 146 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 147 g_free(nodename); 148 } 149 nodename = g_strdup_printf("/soc/clint@%lx", 150 (long)memmap[SIFIVE_U_CLINT].base); 151 qemu_fdt_add_subnode(fdt, nodename); 152 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 153 qemu_fdt_setprop_cells(fdt, nodename, "reg", 154 0x0, memmap[SIFIVE_U_CLINT].base, 155 0x0, memmap[SIFIVE_U_CLINT].size); 156 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 157 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 158 g_free(cells); 159 g_free(nodename); 160 161 plic_phandle = phandle++; 162 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 163 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 164 nodename = 165 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 166 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 167 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 168 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 169 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 170 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 171 g_free(nodename); 172 } 173 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 174 (long)memmap[SIFIVE_U_PLIC].base); 175 qemu_fdt_add_subnode(fdt, nodename); 176 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 177 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 178 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 179 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 180 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 181 qemu_fdt_setprop_cells(fdt, nodename, "reg", 182 0x0, memmap[SIFIVE_U_PLIC].base, 183 0x0, memmap[SIFIVE_U_PLIC].size); 184 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 185 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); 186 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 187 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); 188 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); 189 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 190 g_free(cells); 191 g_free(nodename); 192 193 ethclk_phandle = phandle++; 194 nodename = g_strdup_printf("/soc/ethclk"); 195 qemu_fdt_add_subnode(fdt, nodename); 196 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 197 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 198 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 199 SIFIVE_U_GEM_CLOCK_FREQ); 200 qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); 201 qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle); 202 ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); 203 g_free(nodename); 204 205 nodename = g_strdup_printf("/soc/ethernet@%lx", 206 (long)memmap[SIFIVE_U_GEM].base); 207 qemu_fdt_add_subnode(fdt, nodename); 208 qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); 209 qemu_fdt_setprop_cells(fdt, nodename, "reg", 210 0x0, memmap[SIFIVE_U_GEM].base, 211 0x0, memmap[SIFIVE_U_GEM].size); 212 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 213 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 214 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 215 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 216 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 217 ethclk_phandle, ethclk_phandle, ethclk_phandle); 218 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 219 sizeof(ethclk_names)); 220 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); 221 qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); 222 g_free(nodename); 223 224 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 225 (long)memmap[SIFIVE_U_GEM].base); 226 qemu_fdt_add_subnode(fdt, nodename); 227 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); 228 g_free(nodename); 229 230 uartclk_phandle = phandle++; 231 nodename = g_strdup_printf("/soc/uartclk"); 232 qemu_fdt_add_subnode(fdt, nodename); 233 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 234 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 235 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); 236 qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); 237 qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", uartclk_phandle); 238 uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); 239 g_free(nodename); 240 241 nodename = g_strdup_printf("/soc/uart@%lx", 242 (long)memmap[SIFIVE_U_UART0].base); 243 qemu_fdt_add_subnode(fdt, nodename); 244 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 245 qemu_fdt_setprop_cells(fdt, nodename, "reg", 246 0x0, memmap[SIFIVE_U_UART0].base, 247 0x0, memmap[SIFIVE_U_UART0].size); 248 qemu_fdt_setprop_cells(fdt, nodename, "clocks", uartclk_phandle); 249 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 250 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 251 252 qemu_fdt_add_subnode(fdt, "/chosen"); 253 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 254 if (cmdline) { 255 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 256 } 257 258 qemu_fdt_add_subnode(fdt, "/aliases"); 259 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 260 261 g_free(nodename); 262 263 return fdt; 264 } 265 266 static void riscv_sifive_u_init(MachineState *machine) 267 { 268 const struct MemmapEntry *memmap = sifive_u_memmap; 269 void *fdt; 270 271 SiFiveUState *s = g_new0(SiFiveUState, 1); 272 MemoryRegion *system_memory = get_system_memory(); 273 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 274 int i; 275 276 /* Initialize SoC */ 277 object_initialize_child(OBJECT(machine), "soc", &s->soc, 278 sizeof(s->soc), TYPE_RISCV_U_SOC, 279 &error_abort, NULL); 280 object_property_set_bool(OBJECT(&s->soc), true, "realized", 281 &error_abort); 282 283 /* register RAM */ 284 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 285 machine->ram_size, &error_fatal); 286 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 287 main_mem); 288 289 /* create device tree */ 290 fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 291 292 riscv_find_and_load_firmware(machine, BIOS_FILENAME, 293 memmap[SIFIVE_U_DRAM].base); 294 295 if (machine->kernel_filename) { 296 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); 297 298 if (machine->initrd_filename) { 299 hwaddr start; 300 hwaddr end = riscv_load_initrd(machine->initrd_filename, 301 machine->ram_size, kernel_entry, 302 &start); 303 qemu_fdt_setprop_cell(fdt, "/chosen", 304 "linux,initrd-start", start); 305 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 306 end); 307 } 308 } 309 310 /* reset vector */ 311 uint32_t reset_vec[8] = { 312 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 313 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 314 0xf1402573, /* csrr a0, mhartid */ 315 #if defined(TARGET_RISCV32) 316 0x0182a283, /* lw t0, 24(t0) */ 317 #elif defined(TARGET_RISCV64) 318 0x0182b283, /* ld t0, 24(t0) */ 319 #endif 320 0x00028067, /* jr t0 */ 321 0x00000000, 322 memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ 323 0x00000000, 324 /* dtb: */ 325 }; 326 327 /* copy in the reset vector in little_endian byte order */ 328 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 329 reset_vec[i] = cpu_to_le32(reset_vec[i]); 330 } 331 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 332 memmap[SIFIVE_U_MROM].base, &address_space_memory); 333 334 /* copy in the device tree */ 335 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 336 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 337 error_report("not enough space to store device-tree"); 338 exit(1); 339 } 340 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 341 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 342 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 343 &address_space_memory); 344 } 345 346 static void riscv_sifive_u_soc_init(Object *obj) 347 { 348 MachineState *ms = MACHINE(qdev_get_machine()); 349 SiFiveUSoCState *s = RISCV_U_SOC(obj); 350 351 object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), 352 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 353 object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", 354 &error_abort); 355 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 356 &error_abort); 357 358 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), 359 TYPE_CADENCE_GEM); 360 } 361 362 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 363 { 364 MachineState *ms = MACHINE(qdev_get_machine()); 365 SiFiveUSoCState *s = RISCV_U_SOC(dev); 366 const struct MemmapEntry *memmap = sifive_u_memmap; 367 MemoryRegion *system_memory = get_system_memory(); 368 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 369 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; 370 char *plic_hart_config; 371 size_t plic_hart_config_len; 372 int i; 373 Error *err = NULL; 374 NICInfo *nd = &nd_table[0]; 375 376 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 377 &error_abort); 378 379 /* boot rom */ 380 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", 381 memmap[SIFIVE_U_MROM].size, &error_fatal); 382 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 383 mask_rom); 384 385 /* create PLIC hart topology configuration string */ 386 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 387 ms->smp.cpus; 388 plic_hart_config = g_malloc0(plic_hart_config_len); 389 for (i = 0; i < ms->smp.cpus; i++) { 390 if (i != 0) { 391 strncat(plic_hart_config, ",", plic_hart_config_len); 392 } 393 strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, 394 plic_hart_config_len); 395 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 396 } 397 398 /* MMIO */ 399 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 400 plic_hart_config, 401 SIFIVE_U_PLIC_NUM_SOURCES, 402 SIFIVE_U_PLIC_NUM_PRIORITIES, 403 SIFIVE_U_PLIC_PRIORITY_BASE, 404 SIFIVE_U_PLIC_PENDING_BASE, 405 SIFIVE_U_PLIC_ENABLE_BASE, 406 SIFIVE_U_PLIC_ENABLE_STRIDE, 407 SIFIVE_U_PLIC_CONTEXT_BASE, 408 SIFIVE_U_PLIC_CONTEXT_STRIDE, 409 memmap[SIFIVE_U_PLIC].size); 410 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 411 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 412 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 413 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 414 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 415 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 416 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 417 418 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { 419 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); 420 } 421 422 if (nd->used) { 423 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 424 qdev_set_nic_properties(DEVICE(&s->gem), nd); 425 } 426 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 427 &error_abort); 428 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); 429 if (err) { 430 error_propagate(errp, err); 431 return; 432 } 433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 434 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 435 plic_gpios[SIFIVE_U_GEM_IRQ]); 436 } 437 438 static void riscv_sifive_u_machine_init(MachineClass *mc) 439 { 440 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 441 mc->init = riscv_sifive_u_init; 442 /* The real hardware has 5 CPUs, but one of them is a small embedded power 443 * management CPU. 444 */ 445 mc->max_cpus = 4; 446 } 447 448 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) 449 450 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 451 { 452 DeviceClass *dc = DEVICE_CLASS(oc); 453 454 dc->realize = riscv_sifive_u_soc_realize; 455 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 456 dc->user_creatable = false; 457 } 458 459 static const TypeInfo riscv_sifive_u_soc_type_info = { 460 .name = TYPE_RISCV_U_SOC, 461 .parent = TYPE_DEVICE, 462 .instance_size = sizeof(SiFiveUSoCState), 463 .instance_init = riscv_sifive_u_soc_init, 464 .class_init = riscv_sifive_u_soc_class_init, 465 }; 466 467 static void riscv_sifive_u_soc_register_types(void) 468 { 469 type_register_static(&riscv_sifive_u_soc_type_info); 470 } 471 472 type_init(riscv_sifive_u_soc_register_types) 473