1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Provides a board compatible with the SiFive Freedom E SDK: 7 * 8 * 0) UART 9 * 1) CLINT (Core Level Interruptor) 10 * 2) PLIC (Platform Level Interrupt Controller) 11 * 3) PRCI (Power, Reset, Clock, Interrupt) 12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13 * 5) Flash memory emulated as RAM 14 * 15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16 * The OTP ROM and Flash boot code will be emulated in a future version. 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2 or later, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "qemu/error-report.h" 34 #include "qapi/error.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "hw/sysbus.h" 38 #include "hw/char/serial.h" 39 #include "hw/misc/unimp.h" 40 #include "target/riscv/cpu.h" 41 #include "hw/riscv/riscv_hart.h" 42 #include "hw/riscv/sifive_plic.h" 43 #include "hw/riscv/sifive_clint.h" 44 #include "hw/riscv/sifive_uart.h" 45 #include "hw/riscv/sifive_e.h" 46 #include "hw/riscv/sifive_e_prci.h" 47 #include "hw/riscv/boot.h" 48 #include "chardev/char.h" 49 #include "sysemu/arch_init.h" 50 #include "sysemu/sysemu.h" 51 #include "exec/address-spaces.h" 52 53 static const struct MemmapEntry { 54 hwaddr base; 55 hwaddr size; 56 } sifive_e_memmap[] = { 57 [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, 58 [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, 59 [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, 60 [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, 61 [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, 62 [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, 63 [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, 64 [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, 65 [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, 66 [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, 67 [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, 68 [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, 69 [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, 70 [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, 71 [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, 72 [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, 73 [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, 74 [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, 75 [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } 76 }; 77 78 static void riscv_sifive_e_init(MachineState *machine) 79 { 80 const struct MemmapEntry *memmap = sifive_e_memmap; 81 82 SiFiveEState *s = RISCV_E_MACHINE(machine); 83 MemoryRegion *sys_mem = get_system_memory(); 84 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 85 int i; 86 87 /* Initialize SoC */ 88 object_initialize_child(OBJECT(machine), "soc", &s->soc, 89 sizeof(s->soc), TYPE_RISCV_E_SOC, 90 &error_abort, NULL); 91 object_property_set_bool(OBJECT(&s->soc), true, "realized", 92 &error_abort); 93 94 /* Data Tightly Integrated Memory */ 95 memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 96 memmap[SIFIVE_E_DTIM].size, &error_fatal); 97 memory_region_add_subregion(sys_mem, 98 memmap[SIFIVE_E_DTIM].base, main_mem); 99 100 /* Mask ROM reset vector */ 101 uint32_t reset_vec[2] = { 102 0x204002b7, /* 0x1000: lui t0,0x20400 */ 103 0x00028067, /* 0x1004: jr t0 */ 104 }; 105 106 /* copy in the reset vector in little_endian byte order */ 107 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 108 reset_vec[i] = cpu_to_le32(reset_vec[i]); 109 } 110 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 111 memmap[SIFIVE_E_MROM].base, &address_space_memory); 112 113 if (machine->kernel_filename) { 114 riscv_load_kernel(machine->kernel_filename, NULL); 115 } 116 } 117 118 static void sifive_e_machine_instance_init(Object *obj) 119 { 120 } 121 122 static void sifive_e_machine_class_init(ObjectClass *oc, void *data) 123 { 124 MachineClass *mc = MACHINE_CLASS(oc); 125 126 mc->desc = "RISC-V Board compatible with SiFive E SDK"; 127 mc->init = riscv_sifive_e_init; 128 mc->max_cpus = 1; 129 mc->default_cpu_type = SIFIVE_E_CPU; 130 } 131 132 static const TypeInfo sifive_e_machine_typeinfo = { 133 .name = MACHINE_TYPE_NAME("sifive_e"), 134 .parent = TYPE_MACHINE, 135 .class_init = sifive_e_machine_class_init, 136 .instance_init = sifive_e_machine_instance_init, 137 .instance_size = sizeof(SiFiveEState), 138 }; 139 140 static void sifive_e_machine_init_register_types(void) 141 { 142 type_register_static(&sifive_e_machine_typeinfo); 143 } 144 145 type_init(sifive_e_machine_init_register_types) 146 147 static void riscv_sifive_e_soc_init(Object *obj) 148 { 149 MachineState *ms = MACHINE(qdev_get_machine()); 150 SiFiveESoCState *s = RISCV_E_SOC(obj); 151 152 sysbus_init_child_obj(obj, "cpus", &s->cpus, 153 sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); 154 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 155 &error_abort); 156 sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", 157 &s->gpio, sizeof(s->gpio), 158 TYPE_SIFIVE_GPIO); 159 } 160 161 static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) 162 { 163 MachineState *ms = MACHINE(qdev_get_machine()); 164 const struct MemmapEntry *memmap = sifive_e_memmap; 165 Error *err = NULL; 166 167 SiFiveESoCState *s = RISCV_E_SOC(dev); 168 MemoryRegion *sys_mem = get_system_memory(); 169 170 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", 171 &error_abort); 172 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 173 &error_abort); 174 175 /* Mask ROM */ 176 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", 177 memmap[SIFIVE_E_MROM].size, &error_fatal); 178 memory_region_add_subregion(sys_mem, 179 memmap[SIFIVE_E_MROM].base, &s->mask_rom); 180 181 /* MMIO */ 182 s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, 183 (char *)SIFIVE_E_PLIC_HART_CONFIG, 184 SIFIVE_E_PLIC_NUM_SOURCES, 185 SIFIVE_E_PLIC_NUM_PRIORITIES, 186 SIFIVE_E_PLIC_PRIORITY_BASE, 187 SIFIVE_E_PLIC_PENDING_BASE, 188 SIFIVE_E_PLIC_ENABLE_BASE, 189 SIFIVE_E_PLIC_ENABLE_STRIDE, 190 SIFIVE_E_PLIC_CONTEXT_BASE, 191 SIFIVE_E_PLIC_CONTEXT_STRIDE, 192 memmap[SIFIVE_E_PLIC].size); 193 sifive_clint_create(memmap[SIFIVE_E_CLINT].base, 194 memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, 195 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); 196 create_unimplemented_device("riscv.sifive.e.aon", 197 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); 198 sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); 199 200 /* GPIO */ 201 202 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 203 if (err) { 204 error_propagate(errp, err); 205 return; 206 } 207 208 /* Map GPIO registers */ 209 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base); 210 211 /* Pass all GPIOs to the SOC layer so they are available to the board */ 212 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 213 214 /* Connect GPIO interrupts to the PLIC */ 215 for (int i = 0; i < 32; i++) { 216 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 217 qdev_get_gpio_in(DEVICE(s->plic), 218 SIFIVE_E_GPIO0_IRQ0 + i)); 219 } 220 221 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, 222 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 223 create_unimplemented_device("riscv.sifive.e.qspi0", 224 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); 225 create_unimplemented_device("riscv.sifive.e.pwm0", 226 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); 227 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, 228 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 229 create_unimplemented_device("riscv.sifive.e.qspi1", 230 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); 231 create_unimplemented_device("riscv.sifive.e.pwm1", 232 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); 233 create_unimplemented_device("riscv.sifive.e.qspi2", 234 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); 235 create_unimplemented_device("riscv.sifive.e.pwm2", 236 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); 237 238 /* Flash memory */ 239 memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", 240 memmap[SIFIVE_E_XIP].size, &error_fatal); 241 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, 242 &s->xip_mem); 243 } 244 245 static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) 246 { 247 DeviceClass *dc = DEVICE_CLASS(oc); 248 249 dc->realize = riscv_sifive_e_soc_realize; 250 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 251 dc->user_creatable = false; 252 } 253 254 static const TypeInfo riscv_sifive_e_soc_type_info = { 255 .name = TYPE_RISCV_E_SOC, 256 .parent = TYPE_DEVICE, 257 .instance_size = sizeof(SiFiveESoCState), 258 .instance_init = riscv_sifive_e_soc_init, 259 .class_init = riscv_sifive_e_soc_class_init, 260 }; 261 262 static void riscv_sifive_e_soc_register_types(void) 263 { 264 type_register_static(&riscv_sifive_e_soc_type_info); 265 } 266 267 type_init(riscv_sifive_e_soc_register_types) 268