1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Provides a board compatible with the SiFive Freedom E SDK: 7 * 8 * 0) UART 9 * 1) CLINT (Core Level Interruptor) 10 * 2) PLIC (Platform Level Interrupt Controller) 11 * 3) PRCI (Power, Reset, Clock, Interrupt) 12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13 * 5) Flash memory emulated as RAM 14 * 15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16 * The OTP ROM and Flash boot code will be emulated in a future version. 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2 or later, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "qemu/error-report.h" 34 #include "qapi/error.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "hw/sysbus.h" 38 #include "hw/char/serial.h" 39 #include "target/riscv/cpu.h" 40 #include "hw/riscv/riscv_hart.h" 41 #include "hw/riscv/sifive_plic.h" 42 #include "hw/riscv/sifive_clint.h" 43 #include "hw/riscv/sifive_prci.h" 44 #include "hw/riscv/sifive_uart.h" 45 #include "hw/riscv/sifive_e.h" 46 #include "hw/riscv/boot.h" 47 #include "chardev/char.h" 48 #include "sysemu/arch_init.h" 49 #include "exec/address-spaces.h" 50 51 static const struct MemmapEntry { 52 hwaddr base; 53 hwaddr size; 54 } sifive_e_memmap[] = { 55 [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, 56 [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, 57 [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, 58 [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, 59 [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, 60 [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, 61 [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, 62 [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, 63 [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, 64 [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, 65 [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, 66 [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, 67 [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, 68 [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, 69 [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, 70 [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, 71 [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, 72 [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, 73 [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } 74 }; 75 76 static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, 77 uintptr_t offset, uintptr_t length) 78 { 79 MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); 80 memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); 81 memory_region_add_subregion(parent, offset, mock_mmio); 82 } 83 84 static void riscv_sifive_e_init(MachineState *machine) 85 { 86 const struct MemmapEntry *memmap = sifive_e_memmap; 87 88 SiFiveEState *s = g_new0(SiFiveEState, 1); 89 MemoryRegion *sys_mem = get_system_memory(); 90 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 91 int i; 92 93 /* Initialize SoC */ 94 object_initialize_child(OBJECT(machine), "soc", &s->soc, 95 sizeof(s->soc), TYPE_RISCV_E_SOC, 96 &error_abort, NULL); 97 object_property_set_bool(OBJECT(&s->soc), true, "realized", 98 &error_abort); 99 100 /* Data Tightly Integrated Memory */ 101 memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 102 memmap[SIFIVE_E_DTIM].size, &error_fatal); 103 memory_region_add_subregion(sys_mem, 104 memmap[SIFIVE_E_DTIM].base, main_mem); 105 106 /* Mask ROM reset vector */ 107 uint32_t reset_vec[2] = { 108 0x204002b7, /* 0x1000: lui t0,0x20400 */ 109 0x00028067, /* 0x1004: jr t0 */ 110 }; 111 112 /* copy in the reset vector in little_endian byte order */ 113 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 114 reset_vec[i] = cpu_to_le32(reset_vec[i]); 115 } 116 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 117 memmap[SIFIVE_E_MROM].base, &address_space_memory); 118 119 if (machine->kernel_filename) { 120 riscv_load_kernel(machine->kernel_filename); 121 } 122 } 123 124 static void riscv_sifive_e_soc_init(Object *obj) 125 { 126 MachineState *ms = MACHINE(qdev_get_machine()); 127 SiFiveESoCState *s = RISCV_E_SOC(obj); 128 129 object_initialize_child(obj, "cpus", &s->cpus, 130 sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, 131 &error_abort, NULL); 132 object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", 133 &error_abort); 134 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 135 &error_abort); 136 sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", 137 &s->gpio, sizeof(s->gpio), 138 TYPE_SIFIVE_GPIO); 139 } 140 141 static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) 142 { 143 MachineState *ms = MACHINE(qdev_get_machine()); 144 const struct MemmapEntry *memmap = sifive_e_memmap; 145 Error *err = NULL; 146 147 SiFiveESoCState *s = RISCV_E_SOC(dev); 148 MemoryRegion *sys_mem = get_system_memory(); 149 150 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 151 &error_abort); 152 153 /* Mask ROM */ 154 memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom", 155 memmap[SIFIVE_E_MROM].size, &error_fatal); 156 memory_region_add_subregion(sys_mem, 157 memmap[SIFIVE_E_MROM].base, &s->mask_rom); 158 159 /* MMIO */ 160 s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, 161 (char *)SIFIVE_E_PLIC_HART_CONFIG, 162 SIFIVE_E_PLIC_NUM_SOURCES, 163 SIFIVE_E_PLIC_NUM_PRIORITIES, 164 SIFIVE_E_PLIC_PRIORITY_BASE, 165 SIFIVE_E_PLIC_PENDING_BASE, 166 SIFIVE_E_PLIC_ENABLE_BASE, 167 SIFIVE_E_PLIC_ENABLE_STRIDE, 168 SIFIVE_E_PLIC_CONTEXT_BASE, 169 SIFIVE_E_PLIC_CONTEXT_STRIDE, 170 memmap[SIFIVE_E_PLIC].size); 171 sifive_clint_create(memmap[SIFIVE_E_CLINT].base, 172 memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, 173 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 174 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", 175 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); 176 sifive_prci_create(memmap[SIFIVE_E_PRCI].base); 177 178 /* GPIO */ 179 180 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 181 if (err) { 182 error_propagate(errp, err); 183 return; 184 } 185 186 /* Map GPIO registers */ 187 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base); 188 189 /* Pass all GPIOs to the SOC layer so they are available to the board */ 190 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 191 192 /* Connect GPIO interrupts to the PLIC */ 193 for (int i = 0; i < 32; i++) { 194 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 195 qdev_get_gpio_in(DEVICE(s->plic), 196 SIFIVE_E_GPIO0_IRQ0 + i)); 197 } 198 199 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, 200 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 201 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", 202 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); 203 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", 204 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); 205 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, 206 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 207 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", 208 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); 209 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", 210 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); 211 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", 212 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); 213 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", 214 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); 215 216 /* Flash memory */ 217 memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip", 218 memmap[SIFIVE_E_XIP].size, &error_fatal); 219 memory_region_set_readonly(&s->xip_mem, true); 220 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, 221 &s->xip_mem); 222 } 223 224 static void riscv_sifive_e_machine_init(MachineClass *mc) 225 { 226 mc->desc = "RISC-V Board compatible with SiFive E SDK"; 227 mc->init = riscv_sifive_e_init; 228 mc->max_cpus = 1; 229 } 230 231 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) 232 233 static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) 234 { 235 DeviceClass *dc = DEVICE_CLASS(oc); 236 237 dc->realize = riscv_sifive_e_soc_realize; 238 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 239 dc->user_creatable = false; 240 } 241 242 static const TypeInfo riscv_sifive_e_soc_type_info = { 243 .name = TYPE_RISCV_E_SOC, 244 .parent = TYPE_DEVICE, 245 .instance_size = sizeof(SiFiveESoCState), 246 .instance_init = riscv_sifive_e_soc_init, 247 .class_init = riscv_sifive_e_soc_class_init, 248 }; 249 250 static void riscv_sifive_e_soc_register_types(void) 251 { 252 type_register_static(&riscv_sifive_e_soc_type_info); 253 } 254 255 type_init(riscv_sifive_e_soc_register_types) 256