1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Provides a board compatible with the SiFive Freedom E SDK: 7 * 8 * 0) UART 9 * 1) CLINT (Core Level Interruptor) 10 * 2) PLIC (Platform Level Interrupt Controller) 11 * 3) PRCI (Power, Reset, Clock, Interrupt) 12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13 * 5) Flash memory emulated as RAM 14 * 15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16 * The OTP ROM and Flash boot code will be emulated in a future version. 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2 or later, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/cutils.h" 33 #include "qemu/error-report.h" 34 #include "qapi/error.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "hw/sysbus.h" 38 #include "hw/misc/unimp.h" 39 #include "target/riscv/cpu.h" 40 #include "hw/riscv/riscv_hart.h" 41 #include "hw/riscv/sifive_e.h" 42 #include "hw/riscv/boot.h" 43 #include "hw/char/sifive_uart.h" 44 #include "hw/intc/riscv_aclint.h" 45 #include "hw/intc/sifive_plic.h" 46 #include "hw/misc/sifive_e_prci.h" 47 #include "hw/misc/sifive_e_aon.h" 48 #include "chardev/char.h" 49 #include "sysemu/sysemu.h" 50 51 static const MemMapEntry sifive_e_memmap[] = { 52 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 }, 53 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 }, 54 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 }, 55 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 }, 56 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 }, 57 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 }, 58 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 }, 59 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 }, 60 [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 }, 61 [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 }, 62 [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 }, 63 [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 }, 64 [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 }, 65 [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 }, 66 [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 }, 67 [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 }, 68 [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 }, 69 [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 }, 70 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 } 71 }; 72 73 static void sifive_e_machine_init(MachineState *machine) 74 { 75 MachineClass *mc = MACHINE_GET_CLASS(machine); 76 const MemMapEntry *memmap = sifive_e_memmap; 77 78 SiFiveEState *s = RISCV_E_MACHINE(machine); 79 MemoryRegion *sys_mem = get_system_memory(); 80 int i; 81 82 if (machine->ram_size != mc->default_ram_size) { 83 char *sz = size_to_str(mc->default_ram_size); 84 error_report("Invalid RAM size, should be %s", sz); 85 g_free(sz); 86 exit(EXIT_FAILURE); 87 } 88 89 /* Initialize SoC */ 90 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); 91 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 92 93 /* Data Tightly Integrated Memory */ 94 memory_region_add_subregion(sys_mem, 95 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); 96 97 /* Mask ROM reset vector */ 98 uint32_t reset_vec[4]; 99 100 if (s->revb) { 101 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ 102 } else { 103 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ 104 } 105 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ 106 107 reset_vec[0] = reset_vec[3] = 0; 108 109 /* copy in the reset vector in little_endian byte order */ 110 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 111 reset_vec[i] = cpu_to_le32(reset_vec[i]); 112 } 113 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 114 memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); 115 116 if (machine->kernel_filename) { 117 riscv_load_kernel(machine, &s->soc.cpus, 118 memmap[SIFIVE_E_DEV_DTIM].base, 119 false, NULL); 120 } 121 } 122 123 static bool sifive_e_machine_get_revb(Object *obj, Error **errp) 124 { 125 SiFiveEState *s = RISCV_E_MACHINE(obj); 126 127 return s->revb; 128 } 129 130 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp) 131 { 132 SiFiveEState *s = RISCV_E_MACHINE(obj); 133 134 s->revb = value; 135 } 136 137 static void sifive_e_machine_instance_init(Object *obj) 138 { 139 SiFiveEState *s = RISCV_E_MACHINE(obj); 140 141 s->revb = false; 142 } 143 144 static void sifive_e_machine_class_init(ObjectClass *oc, void *data) 145 { 146 MachineClass *mc = MACHINE_CLASS(oc); 147 148 mc->desc = "RISC-V Board compatible with SiFive E SDK"; 149 mc->init = sifive_e_machine_init; 150 mc->max_cpus = 1; 151 mc->default_cpu_type = SIFIVE_E_CPU; 152 mc->default_ram_id = "riscv.sifive.e.ram"; 153 mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; 154 155 object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb, 156 sifive_e_machine_set_revb); 157 object_class_property_set_description(oc, "revb", 158 "Set on to tell QEMU that it should model " 159 "the revB HiFive1 board"); 160 } 161 162 static const TypeInfo sifive_e_machine_typeinfo = { 163 .name = MACHINE_TYPE_NAME("sifive_e"), 164 .parent = TYPE_MACHINE, 165 .class_init = sifive_e_machine_class_init, 166 .instance_init = sifive_e_machine_instance_init, 167 .instance_size = sizeof(SiFiveEState), 168 }; 169 170 static void sifive_e_machine_init_register_types(void) 171 { 172 type_register_static(&sifive_e_machine_typeinfo); 173 } 174 175 type_init(sifive_e_machine_init_register_types) 176 177 static void sifive_e_soc_init(Object *obj) 178 { 179 MachineState *ms = MACHINE(qdev_get_machine()); 180 SiFiveESoCState *s = RISCV_E_SOC(obj); 181 182 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 183 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 184 &error_abort); 185 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); 186 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, 187 TYPE_SIFIVE_GPIO); 188 object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, 189 TYPE_SIFIVE_E_AON); 190 } 191 192 static void sifive_e_soc_realize(DeviceState *dev, Error **errp) 193 { 194 MachineState *ms = MACHINE(qdev_get_machine()); 195 const MemMapEntry *memmap = sifive_e_memmap; 196 SiFiveESoCState *s = RISCV_E_SOC(dev); 197 MemoryRegion *sys_mem = get_system_memory(); 198 199 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 200 &error_abort); 201 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); 202 203 /* Mask ROM */ 204 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", 205 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); 206 memory_region_add_subregion(sys_mem, 207 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); 208 209 /* MMIO */ 210 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, 211 (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, 212 SIFIVE_E_PLIC_NUM_SOURCES, 213 SIFIVE_E_PLIC_NUM_PRIORITIES, 214 SIFIVE_E_PLIC_PRIORITY_BASE, 215 SIFIVE_E_PLIC_PENDING_BASE, 216 SIFIVE_E_PLIC_ENABLE_BASE, 217 SIFIVE_E_PLIC_ENABLE_STRIDE, 218 SIFIVE_E_PLIC_CONTEXT_BASE, 219 SIFIVE_E_PLIC_CONTEXT_STRIDE, 220 memmap[SIFIVE_E_DEV_PLIC].size); 221 riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, 222 0, ms->smp.cpus, false); 223 riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + 224 RISCV_ACLINT_SWI_SIZE, 225 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 226 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 227 SIFIVE_E_LFCLK_DEFAULT_FREQ, false); 228 sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); 229 230 /* AON */ 231 232 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) { 233 return; 234 } 235 236 /* Map AON registers */ 237 sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base); 238 239 /* GPIO */ 240 241 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 242 return; 243 } 244 245 /* Map GPIO registers */ 246 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base); 247 248 /* Pass all GPIOs to the SOC layer so they are available to the board */ 249 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 250 251 /* Connect GPIO interrupts to the PLIC */ 252 for (int i = 0; i < 32; i++) { 253 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 254 qdev_get_gpio_in(DEVICE(s->plic), 255 SIFIVE_E_GPIO0_IRQ0 + i)); 256 } 257 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0, 258 qdev_get_gpio_in(DEVICE(s->plic), 259 SIFIVE_E_AON_WDT_IRQ)); 260 261 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, 262 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 263 create_unimplemented_device("riscv.sifive.e.qspi0", 264 memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); 265 create_unimplemented_device("riscv.sifive.e.pwm0", 266 memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); 267 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, 268 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 269 create_unimplemented_device("riscv.sifive.e.qspi1", 270 memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); 271 create_unimplemented_device("riscv.sifive.e.pwm1", 272 memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); 273 create_unimplemented_device("riscv.sifive.e.qspi2", 274 memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); 275 create_unimplemented_device("riscv.sifive.e.pwm2", 276 memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size); 277 278 /* Flash memory */ 279 memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", 280 memmap[SIFIVE_E_DEV_XIP].size, &error_fatal); 281 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base, 282 &s->xip_mem); 283 } 284 285 static void sifive_e_soc_class_init(ObjectClass *oc, void *data) 286 { 287 DeviceClass *dc = DEVICE_CLASS(oc); 288 289 dc->realize = sifive_e_soc_realize; 290 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 291 dc->user_creatable = false; 292 } 293 294 static const TypeInfo sifive_e_soc_type_info = { 295 .name = TYPE_RISCV_E_SOC, 296 .parent = TYPE_DEVICE, 297 .instance_size = sizeof(SiFiveESoCState), 298 .instance_init = sifive_e_soc_init, 299 .class_init = sifive_e_soc_class_init, 300 }; 301 302 static void sifive_e_soc_register_types(void) 303 { 304 type_register_static(&sifive_e_soc_type_info); 305 } 306 307 type_init(sifive_e_soc_register_types) 308