1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Provides a board compatible with the SiFive Freedom E SDK: 7 * 8 * 0) UART 9 * 1) CLINT (Core Level Interruptor) 10 * 2) PLIC (Platform Level Interrupt Controller) 11 * 3) PRCI (Power, Reset, Clock, Interrupt) 12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13 * 5) Flash memory emulated as RAM 14 * 15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16 * The OTP ROM and Flash boot code will be emulated in a future version. 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2 or later, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "qemu/error-report.h" 34 #include "qapi/error.h" 35 #include "hw/hw.h" 36 #include "hw/boards.h" 37 #include "hw/loader.h" 38 #include "hw/sysbus.h" 39 #include "hw/char/serial.h" 40 #include "target/riscv/cpu.h" 41 #include "hw/riscv/riscv_hart.h" 42 #include "hw/riscv/sifive_plic.h" 43 #include "hw/riscv/sifive_clint.h" 44 #include "hw/riscv/sifive_prci.h" 45 #include "hw/riscv/sifive_uart.h" 46 #include "hw/riscv/sifive_e.h" 47 #include "chardev/char.h" 48 #include "sysemu/arch_init.h" 49 #include "exec/address-spaces.h" 50 #include "elf.h" 51 52 static const struct MemmapEntry { 53 hwaddr base; 54 hwaddr size; 55 } sifive_e_memmap[] = { 56 [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, 57 [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, 58 [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, 59 [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, 60 [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, 61 [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, 62 [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, 63 [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, 64 [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, 65 [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, 66 [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, 67 [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, 68 [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, 69 [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, 70 [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, 71 [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, 72 [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, 73 [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, 74 [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } 75 }; 76 77 static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) 78 { 79 int i; 80 for (i = 0; i < (len >> 2); i++) { 81 stl_phys(&address_space_memory, pa + (i << 2), rom[i]); 82 } 83 } 84 85 static uint64_t identity_translate(void *opaque, uint64_t addr) 86 { 87 return addr; 88 } 89 90 static uint64_t load_kernel(const char *kernel_filename) 91 { 92 uint64_t kernel_entry, kernel_high; 93 94 if (load_elf(kernel_filename, identity_translate, NULL, 95 &kernel_entry, NULL, &kernel_high, 96 0, ELF_MACHINE, 1, 0) < 0) { 97 error_report("qemu: could not load kernel '%s'", kernel_filename); 98 exit(1); 99 } 100 return kernel_entry; 101 } 102 103 static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, 104 uintptr_t offset, uintptr_t length) 105 { 106 MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); 107 memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); 108 memory_region_add_subregion(parent, offset, mock_mmio); 109 } 110 111 static void riscv_sifive_e_init(MachineState *machine) 112 { 113 const struct MemmapEntry *memmap = sifive_e_memmap; 114 115 SiFiveEState *s = g_new0(SiFiveEState, 1); 116 MemoryRegion *sys_mem = get_system_memory(); 117 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 118 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 119 MemoryRegion *xip_mem = g_new(MemoryRegion, 1); 120 121 /* Initialize SOC */ 122 object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); 123 object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 124 &error_abort); 125 object_property_set_str(OBJECT(&s->soc), SIFIVE_E_CPU, "cpu-type", 126 &error_abort); 127 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 128 &error_abort); 129 object_property_set_bool(OBJECT(&s->soc), true, "realized", 130 &error_abort); 131 132 /* Data Tightly Integrated Memory */ 133 memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 134 memmap[SIFIVE_E_DTIM].size, &error_fatal); 135 memory_region_add_subregion(sys_mem, 136 memmap[SIFIVE_E_DTIM].base, main_mem); 137 138 /* Mask ROM */ 139 memory_region_init_ram(mask_rom, NULL, "riscv.sifive.e.mrom", 140 memmap[SIFIVE_E_MROM].size, &error_fatal); 141 memory_region_add_subregion(sys_mem, 142 memmap[SIFIVE_E_MROM].base, mask_rom); 143 144 /* MMIO */ 145 s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, 146 (char *)SIFIVE_E_PLIC_HART_CONFIG, 147 SIFIVE_E_PLIC_NUM_SOURCES, 148 SIFIVE_E_PLIC_NUM_PRIORITIES, 149 SIFIVE_E_PLIC_PRIORITY_BASE, 150 SIFIVE_E_PLIC_PENDING_BASE, 151 SIFIVE_E_PLIC_ENABLE_BASE, 152 SIFIVE_E_PLIC_ENABLE_STRIDE, 153 SIFIVE_E_PLIC_CONTEXT_BASE, 154 SIFIVE_E_PLIC_CONTEXT_STRIDE, 155 memmap[SIFIVE_E_PLIC].size); 156 sifive_clint_create(memmap[SIFIVE_E_CLINT].base, 157 memmap[SIFIVE_E_CLINT].size, smp_cpus, 158 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 159 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", 160 memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); 161 sifive_prci_create(memmap[SIFIVE_E_PRCI].base); 162 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0", 163 memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size); 164 sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, 165 serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); 166 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", 167 memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); 168 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", 169 memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); 170 /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, 171 serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ 172 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", 173 memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); 174 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", 175 memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); 176 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", 177 memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); 178 sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", 179 memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); 180 181 /* Flash memory */ 182 memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip", 183 memmap[SIFIVE_E_XIP].size, &error_fatal); 184 memory_region_set_readonly(xip_mem, true); 185 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem); 186 187 /* Mask ROM reset vector */ 188 uint32_t reset_vec[2] = { 189 0x204002b7, /* 0x1000: lui t0,0x20400 */ 190 0x00028067, /* 0x1004: jr t0 */ 191 }; 192 193 /* copy in the reset vector */ 194 copy_le32_to_phys(memmap[SIFIVE_E_MROM].base, reset_vec, sizeof(reset_vec)); 195 memory_region_set_readonly(mask_rom, true); 196 197 if (machine->kernel_filename) { 198 load_kernel(machine->kernel_filename); 199 } 200 } 201 202 static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) 203 { 204 return 0; 205 } 206 207 static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) 208 { 209 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 210 k->init = riscv_sifive_e_sysbus_device_init; 211 } 212 213 static const TypeInfo riscv_sifive_e_device = { 214 .name = TYPE_SIFIVE_E, 215 .parent = TYPE_SYS_BUS_DEVICE, 216 .instance_size = sizeof(SiFiveEState), 217 .class_init = riscv_sifive_e_class_init, 218 }; 219 220 static void riscv_sifive_e_machine_init(MachineClass *mc) 221 { 222 mc->desc = "RISC-V Board compatible with SiFive E SDK"; 223 mc->init = riscv_sifive_e_init; 224 mc->max_cpus = 1; 225 } 226 227 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) 228 229 static void riscv_sifive_e_register_types(void) 230 { 231 type_register_static(&riscv_sifive_e_device); 232 } 233 234 type_init(riscv_sifive_e_register_types); 235