xref: /openbmc/qemu/hw/riscv/sifive_e.c (revision 19f4ed36)
1 /*
2  * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  *
6  * Provides a board compatible with the SiFive Freedom E SDK:
7  *
8  * 0) UART
9  * 1) CLINT (Core Level Interruptor)
10  * 2) PLIC (Platform Level Interrupt Controller)
11  * 3) PRCI (Power, Reset, Clock, Interrupt)
12  * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
13  * 5) Flash memory emulated as RAM
14  *
15  * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
16  * The OTP ROM and Flash boot code will be emulated in a future version.
17  *
18  * This program is free software; you can redistribute it and/or modify it
19  * under the terms and conditions of the GNU General Public License,
20  * version 2 or later, as published by the Free Software Foundation.
21  *
22  * This program is distributed in the hope it will be useful, but WITHOUT
23  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
25  * more details.
26  *
27  * You should have received a copy of the GNU General Public License along with
28  * this program.  If not, see <http://www.gnu.org/licenses/>.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu/error-report.h"
33 #include "qapi/error.h"
34 #include "hw/boards.h"
35 #include "hw/loader.h"
36 #include "hw/sysbus.h"
37 #include "hw/char/serial.h"
38 #include "hw/misc/unimp.h"
39 #include "target/riscv/cpu.h"
40 #include "hw/riscv/riscv_hart.h"
41 #include "hw/riscv/sifive_e.h"
42 #include "hw/riscv/boot.h"
43 #include "hw/char/sifive_uart.h"
44 #include "hw/intc/sifive_clint.h"
45 #include "hw/intc/sifive_plic.h"
46 #include "hw/misc/sifive_e_prci.h"
47 #include "chardev/char.h"
48 #include "sysemu/arch_init.h"
49 #include "sysemu/sysemu.h"
50 #include "exec/address-spaces.h"
51 
52 static MemMapEntry sifive_e_memmap[] = {
53     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
54     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
55     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
56     [SIFIVE_E_DEV_CLINT] =    {  0x2000000,    0x10000 },
57     [SIFIVE_E_DEV_PLIC] =     {  0xc000000,  0x4000000 },
58     [SIFIVE_E_DEV_AON] =      { 0x10000000,     0x8000 },
59     [SIFIVE_E_DEV_PRCI] =     { 0x10008000,     0x8000 },
60     [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000,     0x1000 },
61     [SIFIVE_E_DEV_GPIO0] =    { 0x10012000,     0x1000 },
62     [SIFIVE_E_DEV_UART0] =    { 0x10013000,     0x1000 },
63     [SIFIVE_E_DEV_QSPI0] =    { 0x10014000,     0x1000 },
64     [SIFIVE_E_DEV_PWM0] =     { 0x10015000,     0x1000 },
65     [SIFIVE_E_DEV_UART1] =    { 0x10023000,     0x1000 },
66     [SIFIVE_E_DEV_QSPI1] =    { 0x10024000,     0x1000 },
67     [SIFIVE_E_DEV_PWM1] =     { 0x10025000,     0x1000 },
68     [SIFIVE_E_DEV_QSPI2] =    { 0x10034000,     0x1000 },
69     [SIFIVE_E_DEV_PWM2] =     { 0x10035000,     0x1000 },
70     [SIFIVE_E_DEV_XIP] =      { 0x20000000, 0x20000000 },
71     [SIFIVE_E_DEV_DTIM] =     { 0x80000000,     0x4000 }
72 };
73 
74 static void sifive_e_machine_init(MachineState *machine)
75 {
76     const MemMapEntry *memmap = sifive_e_memmap;
77 
78     SiFiveEState *s = RISCV_E_MACHINE(machine);
79     MemoryRegion *sys_mem = get_system_memory();
80     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
81     int i;
82 
83     /* Initialize SoC */
84     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
85     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
86 
87     /* Data Tightly Integrated Memory */
88     memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
89         memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
90     memory_region_add_subregion(sys_mem,
91         memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
92 
93     /* Mask ROM reset vector */
94     uint32_t reset_vec[4];
95 
96     if (s->revb) {
97         reset_vec[1] = 0x200102b7;  /* 0x1004: lui     t0,0x20010 */
98     } else {
99         reset_vec[1] = 0x204002b7;  /* 0x1004: lui     t0,0x20400 */
100     }
101     reset_vec[2] = 0x00028067;      /* 0x1008: jr      t0 */
102 
103     reset_vec[0] = reset_vec[3] = 0;
104 
105     /* copy in the reset vector in little_endian byte order */
106     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
107         reset_vec[i] = cpu_to_le32(reset_vec[i]);
108     }
109     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
110                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
111 
112     if (machine->kernel_filename) {
113         riscv_load_kernel(machine->kernel_filename,
114                           memmap[SIFIVE_E_DEV_DTIM].base, NULL);
115     }
116 }
117 
118 static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
119 {
120     SiFiveEState *s = RISCV_E_MACHINE(obj);
121 
122     return s->revb;
123 }
124 
125 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
126 {
127     SiFiveEState *s = RISCV_E_MACHINE(obj);
128 
129     s->revb = value;
130 }
131 
132 static void sifive_e_machine_instance_init(Object *obj)
133 {
134     SiFiveEState *s = RISCV_E_MACHINE(obj);
135 
136     s->revb = false;
137 }
138 
139 static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
140 {
141     MachineClass *mc = MACHINE_CLASS(oc);
142 
143     mc->desc = "RISC-V Board compatible with SiFive E SDK";
144     mc->init = sifive_e_machine_init;
145     mc->max_cpus = 1;
146     mc->default_cpu_type = SIFIVE_E_CPU;
147 
148     object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
149                                    sifive_e_machine_set_revb);
150     object_class_property_set_description(oc, "revb",
151                                           "Set on to tell QEMU that it should model "
152                                           "the revB HiFive1 board");
153 }
154 
155 static const TypeInfo sifive_e_machine_typeinfo = {
156     .name       = MACHINE_TYPE_NAME("sifive_e"),
157     .parent     = TYPE_MACHINE,
158     .class_init = sifive_e_machine_class_init,
159     .instance_init = sifive_e_machine_instance_init,
160     .instance_size = sizeof(SiFiveEState),
161 };
162 
163 static void sifive_e_machine_init_register_types(void)
164 {
165     type_register_static(&sifive_e_machine_typeinfo);
166 }
167 
168 type_init(sifive_e_machine_init_register_types)
169 
170 static void sifive_e_soc_init(Object *obj)
171 {
172     MachineState *ms = MACHINE(qdev_get_machine());
173     SiFiveESoCState *s = RISCV_E_SOC(obj);
174 
175     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
176     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
177                             &error_abort);
178     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
179     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
180                             TYPE_SIFIVE_GPIO);
181 }
182 
183 static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
184 {
185     MachineState *ms = MACHINE(qdev_get_machine());
186     const MemMapEntry *memmap = sifive_e_memmap;
187     SiFiveESoCState *s = RISCV_E_SOC(dev);
188     MemoryRegion *sys_mem = get_system_memory();
189 
190     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
191                             &error_abort);
192     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
193 
194     /* Mask ROM */
195     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
196                            memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
197     memory_region_add_subregion(sys_mem,
198         memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
199 
200     /* MMIO */
201     s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
202         (char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
203         SIFIVE_E_PLIC_NUM_SOURCES,
204         SIFIVE_E_PLIC_NUM_PRIORITIES,
205         SIFIVE_E_PLIC_PRIORITY_BASE,
206         SIFIVE_E_PLIC_PENDING_BASE,
207         SIFIVE_E_PLIC_ENABLE_BASE,
208         SIFIVE_E_PLIC_ENABLE_STRIDE,
209         SIFIVE_E_PLIC_CONTEXT_BASE,
210         SIFIVE_E_PLIC_CONTEXT_STRIDE,
211         memmap[SIFIVE_E_DEV_PLIC].size);
212     sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
213         memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
214         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
215         SIFIVE_CLINT_TIMEBASE_FREQ, false);
216     create_unimplemented_device("riscv.sifive.e.aon",
217         memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
218     sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
219 
220     /* GPIO */
221 
222     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
223         return;
224     }
225 
226     /* Map GPIO registers */
227     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
228 
229     /* Pass all GPIOs to the SOC layer so they are available to the board */
230     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
231 
232     /* Connect GPIO interrupts to the PLIC */
233     for (int i = 0; i < 32; i++) {
234         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
235                            qdev_get_gpio_in(DEVICE(s->plic),
236                                             SIFIVE_E_GPIO0_IRQ0 + i));
237     }
238 
239     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
240         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
241     create_unimplemented_device("riscv.sifive.e.qspi0",
242         memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
243     create_unimplemented_device("riscv.sifive.e.pwm0",
244         memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
245     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
246         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
247     create_unimplemented_device("riscv.sifive.e.qspi1",
248         memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
249     create_unimplemented_device("riscv.sifive.e.pwm1",
250         memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
251     create_unimplemented_device("riscv.sifive.e.qspi2",
252         memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
253     create_unimplemented_device("riscv.sifive.e.pwm2",
254         memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
255 
256     /* Flash memory */
257     memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
258                            memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
259     memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
260         &s->xip_mem);
261 }
262 
263 static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
264 {
265     DeviceClass *dc = DEVICE_CLASS(oc);
266 
267     dc->realize = sifive_e_soc_realize;
268     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
269     dc->user_creatable = false;
270 }
271 
272 static const TypeInfo sifive_e_soc_type_info = {
273     .name = TYPE_RISCV_E_SOC,
274     .parent = TYPE_DEVICE,
275     .instance_size = sizeof(SiFiveESoCState),
276     .instance_init = sifive_e_soc_init,
277     .class_init = sifive_e_soc_class_init,
278 };
279 
280 static void sifive_e_soc_register_types(void)
281 {
282     type_register_static(&sifive_e_soc_type_info);
283 }
284 
285 type_init(sifive_e_soc_register_types)
286