1eb637edbSMichael Clark /* 2eb637edbSMichael Clark * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3eb637edbSMichael Clark * 4eb637edbSMichael Clark * Copyright (c) 2017 SiFive, Inc. 5eb637edbSMichael Clark * 6eb637edbSMichael Clark * Provides a board compatible with the SiFive Freedom E SDK: 7eb637edbSMichael Clark * 8eb637edbSMichael Clark * 0) UART 9eb637edbSMichael Clark * 1) CLINT (Core Level Interruptor) 10eb637edbSMichael Clark * 2) PLIC (Platform Level Interrupt Controller) 11eb637edbSMichael Clark * 3) PRCI (Power, Reset, Clock, Interrupt) 12eb637edbSMichael Clark * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13eb637edbSMichael Clark * 5) Flash memory emulated as RAM 14eb637edbSMichael Clark * 15eb637edbSMichael Clark * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16eb637edbSMichael Clark * The OTP ROM and Flash boot code will be emulated in a future version. 17eb637edbSMichael Clark * 18eb637edbSMichael Clark * This program is free software; you can redistribute it and/or modify it 19eb637edbSMichael Clark * under the terms and conditions of the GNU General Public License, 20eb637edbSMichael Clark * version 2 or later, as published by the Free Software Foundation. 21eb637edbSMichael Clark * 22eb637edbSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 23eb637edbSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24eb637edbSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25eb637edbSMichael Clark * more details. 26eb637edbSMichael Clark * 27eb637edbSMichael Clark * You should have received a copy of the GNU General Public License along with 28eb637edbSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 29eb637edbSMichael Clark */ 30eb637edbSMichael Clark 31eb637edbSMichael Clark #include "qemu/osdep.h" 32eb637edbSMichael Clark #include "qemu/error-report.h" 33eb637edbSMichael Clark #include "qapi/error.h" 34eb637edbSMichael Clark #include "hw/boards.h" 35eb637edbSMichael Clark #include "hw/loader.h" 36eb637edbSMichael Clark #include "hw/sysbus.h" 37eb637edbSMichael Clark #include "hw/char/serial.h" 3868c9a9b3SBin Meng #include "hw/misc/unimp.h" 39eb637edbSMichael Clark #include "target/riscv/cpu.h" 40eb637edbSMichael Clark #include "hw/riscv/riscv_hart.h" 41eb637edbSMichael Clark #include "hw/riscv/sifive_e.h" 420ac24d56SAlistair Francis #include "hw/riscv/boot.h" 43b609b7e3SBin Meng #include "hw/char/sifive_uart.h" 44cc63a182SAnup Patel #include "hw/intc/riscv_aclint.h" 4584fcf3c1SBin Meng #include "hw/intc/sifive_plic.h" 4689ece6f7SBin Meng #include "hw/misc/sifive_e_prci.h" 47eb637edbSMichael Clark #include "chardev/char.h" 4846517dd4SMarkus Armbruster #include "sysemu/sysemu.h" 49eb637edbSMichael Clark 503de70cecSBin Meng static const MemMapEntry sifive_e_memmap[] = { 515488f276SEduardo Habkost [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 }, 525488f276SEduardo Habkost [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 }, 535488f276SEduardo Habkost [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 }, 545488f276SEduardo Habkost [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 }, 555488f276SEduardo Habkost [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 }, 565488f276SEduardo Habkost [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 }, 575488f276SEduardo Habkost [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 }, 585488f276SEduardo Habkost [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 }, 595488f276SEduardo Habkost [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 }, 605488f276SEduardo Habkost [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 }, 615488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 }, 625488f276SEduardo Habkost [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 }, 635488f276SEduardo Habkost [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 }, 645488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 }, 655488f276SEduardo Habkost [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 }, 665488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 }, 675488f276SEduardo Habkost [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 }, 685488f276SEduardo Habkost [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 }, 695488f276SEduardo Habkost [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 } 70eb637edbSMichael Clark }; 71eb637edbSMichael Clark 728f8c6c1aSBin Meng static void sifive_e_machine_init(MachineState *machine) 73eb637edbSMichael Clark { 7473261285SBin Meng const MemMapEntry *memmap = sifive_e_memmap; 75eb637edbSMichael Clark 760869490bSAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(machine); 77eb637edbSMichael Clark MemoryRegion *sys_mem = get_system_memory(); 78eb637edbSMichael Clark MemoryRegion *main_mem = g_new(MemoryRegion, 1); 795aec3247SMichael Clark int i; 80eb637edbSMichael Clark 81651cd8b7SAlistair Francis /* Initialize SoC */ 829fc7fc4dSMarkus Armbruster object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); 83ce189ab2SMarkus Armbruster qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 84eb637edbSMichael Clark 85eb637edbSMichael Clark /* Data Tightly Integrated Memory */ 86eb637edbSMichael Clark memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 875488f276SEduardo Habkost memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal); 88eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 895488f276SEduardo Habkost memmap[SIFIVE_E_DEV_DTIM].base, main_mem); 90eb637edbSMichael Clark 91651cd8b7SAlistair Francis /* Mask ROM reset vector */ 92495134b7SBin Meng uint32_t reset_vec[4]; 935a842062SAlistair Francis 945a842062SAlistair Francis if (s->revb) { 95495134b7SBin Meng reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ 965a842062SAlistair Francis } else { 97495134b7SBin Meng reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ 985a842062SAlistair Francis } 99495134b7SBin Meng reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ 100495134b7SBin Meng 101495134b7SBin Meng reset_vec[0] = reset_vec[3] = 0; 102651cd8b7SAlistair Francis 103651cd8b7SAlistair Francis /* copy in the reset vector in little_endian byte order */ 104651cd8b7SAlistair Francis for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 105651cd8b7SAlistair Francis reset_vec[i] = cpu_to_le32(reset_vec[i]); 106651cd8b7SAlistair Francis } 107651cd8b7SAlistair Francis rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 1085488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); 109651cd8b7SAlistair Francis 110651cd8b7SAlistair Francis if (machine->kernel_filename) { 11138bc4e34SAlistair Francis riscv_load_kernel(machine->kernel_filename, 11238bc4e34SAlistair Francis memmap[SIFIVE_E_DEV_DTIM].base, NULL); 113651cd8b7SAlistair Francis } 114651cd8b7SAlistair Francis } 115651cd8b7SAlistair Francis 1165a842062SAlistair Francis static bool sifive_e_machine_get_revb(Object *obj, Error **errp) 1175a842062SAlistair Francis { 1185a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1195a842062SAlistair Francis 1205a842062SAlistair Francis return s->revb; 1215a842062SAlistair Francis } 1225a842062SAlistair Francis 1235a842062SAlistair Francis static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp) 1245a842062SAlistair Francis { 1255a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1265a842062SAlistair Francis 1275a842062SAlistair Francis s->revb = value; 1285a842062SAlistair Francis } 1295a842062SAlistair Francis 1300869490bSAlistair Francis static void sifive_e_machine_instance_init(Object *obj) 1310869490bSAlistair Francis { 1325a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1335a842062SAlistair Francis 1345a842062SAlistair Francis s->revb = false; 1350869490bSAlistair Francis } 1360869490bSAlistair Francis 1370869490bSAlistair Francis static void sifive_e_machine_class_init(ObjectClass *oc, void *data) 1380869490bSAlistair Francis { 1390869490bSAlistair Francis MachineClass *mc = MACHINE_CLASS(oc); 1400869490bSAlistair Francis 1410869490bSAlistair Francis mc->desc = "RISC-V Board compatible with SiFive E SDK"; 1428f8c6c1aSBin Meng mc->init = sifive_e_machine_init; 1430869490bSAlistair Francis mc->max_cpus = 1; 1440869490bSAlistair Francis mc->default_cpu_type = SIFIVE_E_CPU; 145fabbcbd9SEduardo Habkost 146fabbcbd9SEduardo Habkost object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb, 147fabbcbd9SEduardo Habkost sifive_e_machine_set_revb); 148fabbcbd9SEduardo Habkost object_class_property_set_description(oc, "revb", 149fabbcbd9SEduardo Habkost "Set on to tell QEMU that it should model " 150fabbcbd9SEduardo Habkost "the revB HiFive1 board"); 1510869490bSAlistair Francis } 1520869490bSAlistair Francis 1530869490bSAlistair Francis static const TypeInfo sifive_e_machine_typeinfo = { 1540869490bSAlistair Francis .name = MACHINE_TYPE_NAME("sifive_e"), 1550869490bSAlistair Francis .parent = TYPE_MACHINE, 1560869490bSAlistair Francis .class_init = sifive_e_machine_class_init, 1570869490bSAlistair Francis .instance_init = sifive_e_machine_instance_init, 1580869490bSAlistair Francis .instance_size = sizeof(SiFiveEState), 1590869490bSAlistair Francis }; 1600869490bSAlistair Francis 1610869490bSAlistair Francis static void sifive_e_machine_init_register_types(void) 1620869490bSAlistair Francis { 1630869490bSAlistair Francis type_register_static(&sifive_e_machine_typeinfo); 1640869490bSAlistair Francis } 1650869490bSAlistair Francis 1660869490bSAlistair Francis type_init(sifive_e_machine_init_register_types) 1670869490bSAlistair Francis 1688f8c6c1aSBin Meng static void sifive_e_soc_init(Object *obj) 169651cd8b7SAlistair Francis { 170c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 171651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(obj); 172651cd8b7SAlistair Francis 173db873cc5SMarkus Armbruster object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 1745325cc34SMarkus Armbruster object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 175651cd8b7SAlistair Francis &error_abort); 17673f6ed97SBin Meng object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); 177db873cc5SMarkus Armbruster object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, 17830efbf33SFabien Chouteau TYPE_SIFIVE_GPIO); 179651cd8b7SAlistair Francis } 180651cd8b7SAlistair Francis 1818f8c6c1aSBin Meng static void sifive_e_soc_realize(DeviceState *dev, Error **errp) 182651cd8b7SAlistair Francis { 183c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 18473261285SBin Meng const MemMapEntry *memmap = sifive_e_memmap; 185651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(dev); 186651cd8b7SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 187651cd8b7SAlistair Francis 1885325cc34SMarkus Armbruster object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 18974dbba9bSCorey Wharton &error_abort); 190db873cc5SMarkus Armbruster sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 191651cd8b7SAlistair Francis 192eb637edbSMichael Clark /* Mask ROM */ 193414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", 1945488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); 195eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 1965488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); 197eb637edbSMichael Clark 198eb637edbSMichael Clark /* MMIO */ 1995488f276SEduardo Habkost s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, 200f436ecc3SAlistair Francis (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, 201eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_SOURCES, 202eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_PRIORITIES, 203eb637edbSMichael Clark SIFIVE_E_PLIC_PRIORITY_BASE, 204eb637edbSMichael Clark SIFIVE_E_PLIC_PENDING_BASE, 205eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_BASE, 206eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_STRIDE, 207eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_BASE, 208eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_STRIDE, 2095488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PLIC].size); 210*b8fb878aSAnup Patel riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, 211*b8fb878aSAnup Patel 0, ms->smp.cpus, false); 212*b8fb878aSAnup Patel riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + 213*b8fb878aSAnup Patel RISCV_ACLINT_SWI_SIZE, 214*b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 215*b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 216*b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); 21768c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.aon", 2185488f276SEduardo Habkost memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); 2195488f276SEduardo Habkost sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); 22030efbf33SFabien Chouteau 22130efbf33SFabien Chouteau /* GPIO */ 22230efbf33SFabien Chouteau 223668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 22430efbf33SFabien Chouteau return; 22530efbf33SFabien Chouteau } 22630efbf33SFabien Chouteau 22730efbf33SFabien Chouteau /* Map GPIO registers */ 2285488f276SEduardo Habkost sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base); 22930efbf33SFabien Chouteau 23030efbf33SFabien Chouteau /* Pass all GPIOs to the SOC layer so they are available to the board */ 23130efbf33SFabien Chouteau qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 23230efbf33SFabien Chouteau 23330efbf33SFabien Chouteau /* Connect GPIO interrupts to the PLIC */ 23430efbf33SFabien Chouteau for (int i = 0; i < 32; i++) { 23530efbf33SFabien Chouteau sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 23630efbf33SFabien Chouteau qdev_get_gpio_in(DEVICE(s->plic), 23730efbf33SFabien Chouteau SIFIVE_E_GPIO0_IRQ0 + i)); 23830efbf33SFabien Chouteau } 23930efbf33SFabien Chouteau 2405488f276SEduardo Habkost sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, 241647a70a1SAlistair Francis serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 24268c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi0", 2435488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); 24468c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm0", 2455488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); 2465488f276SEduardo Habkost sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, 247194eef09SMichael Clark serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 24868c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi1", 2495488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); 25068c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm1", 2515488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); 25268c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi2", 2535488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); 25468c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm2", 2555488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size); 256eb637edbSMichael Clark 257eb637edbSMichael Clark /* Flash memory */ 258414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", 2595488f276SEduardo Habkost memmap[SIFIVE_E_DEV_XIP].size, &error_fatal); 2605488f276SEduardo Habkost memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base, 261c988de41SPalmer Dabbelt &s->xip_mem); 262eb637edbSMichael Clark } 263eb637edbSMichael Clark 2648f8c6c1aSBin Meng static void sifive_e_soc_class_init(ObjectClass *oc, void *data) 265651cd8b7SAlistair Francis { 266651cd8b7SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc); 267651cd8b7SAlistair Francis 2688f8c6c1aSBin Meng dc->realize = sifive_e_soc_realize; 269651cd8b7SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 270651cd8b7SAlistair Francis dc->user_creatable = false; 271651cd8b7SAlistair Francis } 272651cd8b7SAlistair Francis 2738f8c6c1aSBin Meng static const TypeInfo sifive_e_soc_type_info = { 274651cd8b7SAlistair Francis .name = TYPE_RISCV_E_SOC, 275651cd8b7SAlistair Francis .parent = TYPE_DEVICE, 276651cd8b7SAlistair Francis .instance_size = sizeof(SiFiveESoCState), 2778f8c6c1aSBin Meng .instance_init = sifive_e_soc_init, 2788f8c6c1aSBin Meng .class_init = sifive_e_soc_class_init, 279651cd8b7SAlistair Francis }; 280651cd8b7SAlistair Francis 2818f8c6c1aSBin Meng static void sifive_e_soc_register_types(void) 282651cd8b7SAlistair Francis { 2838f8c6c1aSBin Meng type_register_static(&sifive_e_soc_type_info); 284651cd8b7SAlistair Francis } 285651cd8b7SAlistair Francis 2868f8c6c1aSBin Meng type_init(sifive_e_soc_register_types) 287