1eb637edbSMichael Clark /* 2eb637edbSMichael Clark * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3eb637edbSMichael Clark * 4eb637edbSMichael Clark * Copyright (c) 2017 SiFive, Inc. 5eb637edbSMichael Clark * 6eb637edbSMichael Clark * Provides a board compatible with the SiFive Freedom E SDK: 7eb637edbSMichael Clark * 8eb637edbSMichael Clark * 0) UART 9eb637edbSMichael Clark * 1) CLINT (Core Level Interruptor) 10eb637edbSMichael Clark * 2) PLIC (Platform Level Interrupt Controller) 11eb637edbSMichael Clark * 3) PRCI (Power, Reset, Clock, Interrupt) 12eb637edbSMichael Clark * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13eb637edbSMichael Clark * 5) Flash memory emulated as RAM 14eb637edbSMichael Clark * 15eb637edbSMichael Clark * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16eb637edbSMichael Clark * The OTP ROM and Flash boot code will be emulated in a future version. 17eb637edbSMichael Clark * 18eb637edbSMichael Clark * This program is free software; you can redistribute it and/or modify it 19eb637edbSMichael Clark * under the terms and conditions of the GNU General Public License, 20eb637edbSMichael Clark * version 2 or later, as published by the Free Software Foundation. 21eb637edbSMichael Clark * 22eb637edbSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 23eb637edbSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24eb637edbSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25eb637edbSMichael Clark * more details. 26eb637edbSMichael Clark * 27eb637edbSMichael Clark * You should have received a copy of the GNU General Public License along with 28eb637edbSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 29eb637edbSMichael Clark */ 30eb637edbSMichael Clark 31eb637edbSMichael Clark #include "qemu/osdep.h" 32eb637edbSMichael Clark #include "qemu/log.h" 33eb637edbSMichael Clark #include "qemu/error-report.h" 34eb637edbSMichael Clark #include "qapi/error.h" 35eb637edbSMichael Clark #include "hw/hw.h" 36eb637edbSMichael Clark #include "hw/boards.h" 37eb637edbSMichael Clark #include "hw/loader.h" 38eb637edbSMichael Clark #include "hw/sysbus.h" 39eb637edbSMichael Clark #include "hw/char/serial.h" 40eb637edbSMichael Clark #include "target/riscv/cpu.h" 41eb637edbSMichael Clark #include "hw/riscv/riscv_hart.h" 42eb637edbSMichael Clark #include "hw/riscv/sifive_plic.h" 43eb637edbSMichael Clark #include "hw/riscv/sifive_clint.h" 44eb637edbSMichael Clark #include "hw/riscv/sifive_prci.h" 45eb637edbSMichael Clark #include "hw/riscv/sifive_uart.h" 46eb637edbSMichael Clark #include "hw/riscv/sifive_e.h" 47eb637edbSMichael Clark #include "chardev/char.h" 48eb637edbSMichael Clark #include "sysemu/arch_init.h" 49eb637edbSMichael Clark #include "exec/address-spaces.h" 50eb637edbSMichael Clark #include "elf.h" 51eb637edbSMichael Clark 52eb637edbSMichael Clark static const struct MemmapEntry { 53eb637edbSMichael Clark hwaddr base; 54eb637edbSMichael Clark hwaddr size; 55eb637edbSMichael Clark } sifive_e_memmap[] = { 56eb637edbSMichael Clark [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, 57eb637edbSMichael Clark [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, 58eb637edbSMichael Clark [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, 59eb637edbSMichael Clark [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, 60eb637edbSMichael Clark [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, 61eb637edbSMichael Clark [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, 62eb637edbSMichael Clark [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, 63eb637edbSMichael Clark [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, 64eb637edbSMichael Clark [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, 65eb637edbSMichael Clark [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, 66eb637edbSMichael Clark [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, 67eb637edbSMichael Clark [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, 68eb637edbSMichael Clark [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, 69eb637edbSMichael Clark [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, 70eb637edbSMichael Clark [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, 71eb637edbSMichael Clark [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, 72eb637edbSMichael Clark [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, 73eb637edbSMichael Clark [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, 74eb637edbSMichael Clark [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } 75eb637edbSMichael Clark }; 76eb637edbSMichael Clark 77eb637edbSMichael Clark static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) 78eb637edbSMichael Clark { 79eb637edbSMichael Clark int i; 80eb637edbSMichael Clark for (i = 0; i < (len >> 2); i++) { 81eb637edbSMichael Clark stl_phys(&address_space_memory, pa + (i << 2), rom[i]); 82eb637edbSMichael Clark } 83eb637edbSMichael Clark } 84eb637edbSMichael Clark 85eb637edbSMichael Clark static uint64_t identity_translate(void *opaque, uint64_t addr) 86eb637edbSMichael Clark { 87eb637edbSMichael Clark return addr; 88eb637edbSMichael Clark } 89eb637edbSMichael Clark 90eb637edbSMichael Clark static uint64_t load_kernel(const char *kernel_filename) 91eb637edbSMichael Clark { 92eb637edbSMichael Clark uint64_t kernel_entry, kernel_high; 93eb637edbSMichael Clark 94eb637edbSMichael Clark if (load_elf(kernel_filename, identity_translate, NULL, 95eb637edbSMichael Clark &kernel_entry, NULL, &kernel_high, 96eb637edbSMichael Clark 0, ELF_MACHINE, 1, 0) < 0) { 97eb637edbSMichael Clark error_report("qemu: could not load kernel '%s'", kernel_filename); 98eb637edbSMichael Clark exit(1); 99eb637edbSMichael Clark } 100eb637edbSMichael Clark return kernel_entry; 101eb637edbSMichael Clark } 102eb637edbSMichael Clark 103eb637edbSMichael Clark static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, 104eb637edbSMichael Clark uintptr_t offset, uintptr_t length) 105eb637edbSMichael Clark { 106eb637edbSMichael Clark MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); 107eb637edbSMichael Clark memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); 108eb637edbSMichael Clark memory_region_add_subregion(parent, offset, mock_mmio); 109eb637edbSMichael Clark } 110eb637edbSMichael Clark 111eb637edbSMichael Clark static void riscv_sifive_e_init(MachineState *machine) 112eb637edbSMichael Clark { 113eb637edbSMichael Clark const struct MemmapEntry *memmap = sifive_e_memmap; 114eb637edbSMichael Clark 115eb637edbSMichael Clark SiFiveEState *s = g_new0(SiFiveEState, 1); 116eb637edbSMichael Clark MemoryRegion *sys_mem = get_system_memory(); 117eb637edbSMichael Clark MemoryRegion *main_mem = g_new(MemoryRegion, 1); 118eb637edbSMichael Clark MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 119eb637edbSMichael Clark MemoryRegion *xip_mem = g_new(MemoryRegion, 1); 120eb637edbSMichael Clark 121eb637edbSMichael Clark /* Initialize SOC */ 122eb637edbSMichael Clark object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); 123eb637edbSMichael Clark object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 124eb637edbSMichael Clark &error_abort); 125eb637edbSMichael Clark object_property_set_str(OBJECT(&s->soc), SIFIVE_E_CPU, "cpu-type", 126eb637edbSMichael Clark &error_abort); 127eb637edbSMichael Clark object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 128eb637edbSMichael Clark &error_abort); 129eb637edbSMichael Clark object_property_set_bool(OBJECT(&s->soc), true, "realized", 130eb637edbSMichael Clark &error_abort); 131eb637edbSMichael Clark 132eb637edbSMichael Clark /* Data Tightly Integrated Memory */ 133eb637edbSMichael Clark memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 134eb637edbSMichael Clark memmap[SIFIVE_E_DTIM].size, &error_fatal); 135eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 136eb637edbSMichael Clark memmap[SIFIVE_E_DTIM].base, main_mem); 137eb637edbSMichael Clark 138eb637edbSMichael Clark /* Mask ROM */ 139eb637edbSMichael Clark memory_region_init_ram(mask_rom, NULL, "riscv.sifive.e.mrom", 140eb637edbSMichael Clark memmap[SIFIVE_E_MROM].size, &error_fatal); 141eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 142eb637edbSMichael Clark memmap[SIFIVE_E_MROM].base, mask_rom); 143eb637edbSMichael Clark 144eb637edbSMichael Clark /* MMIO */ 145eb637edbSMichael Clark s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, 146eb637edbSMichael Clark (char *)SIFIVE_E_PLIC_HART_CONFIG, 147eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_SOURCES, 148eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_PRIORITIES, 149eb637edbSMichael Clark SIFIVE_E_PLIC_PRIORITY_BASE, 150eb637edbSMichael Clark SIFIVE_E_PLIC_PENDING_BASE, 151eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_BASE, 152eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_STRIDE, 153eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_BASE, 154eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_STRIDE, 155eb637edbSMichael Clark memmap[SIFIVE_E_PLIC].size); 156eb637edbSMichael Clark sifive_clint_create(memmap[SIFIVE_E_CLINT].base, 157eb637edbSMichael Clark memmap[SIFIVE_E_CLINT].size, smp_cpus, 158eb637edbSMichael Clark SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 159eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", 160eb637edbSMichael Clark memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); 161eb637edbSMichael Clark sifive_prci_create(memmap[SIFIVE_E_PRCI].base); 162eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0", 163eb637edbSMichael Clark memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size); 164eb637edbSMichael Clark sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, 165*9bca0edbSPeter Maydell serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); 166eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", 167eb637edbSMichael Clark memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); 168eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", 169eb637edbSMichael Clark memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); 170eb637edbSMichael Clark /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, 171*9bca0edbSPeter Maydell serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ 172eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", 173eb637edbSMichael Clark memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); 174eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", 175eb637edbSMichael Clark memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); 176eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", 177eb637edbSMichael Clark memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); 178eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", 179eb637edbSMichael Clark memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); 180eb637edbSMichael Clark 181eb637edbSMichael Clark /* Flash memory */ 182eb637edbSMichael Clark memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip", 183eb637edbSMichael Clark memmap[SIFIVE_E_XIP].size, &error_fatal); 184eb637edbSMichael Clark memory_region_set_readonly(xip_mem, true); 185eb637edbSMichael Clark memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem); 186eb637edbSMichael Clark 187eb637edbSMichael Clark /* Mask ROM reset vector */ 188eb637edbSMichael Clark uint32_t reset_vec[2] = { 189eb637edbSMichael Clark 0x204002b7, /* 0x1000: lui t0,0x20400 */ 190eb637edbSMichael Clark 0x00028067, /* 0x1004: jr t0 */ 191eb637edbSMichael Clark }; 192eb637edbSMichael Clark 193eb637edbSMichael Clark /* copy in the reset vector */ 194eb637edbSMichael Clark copy_le32_to_phys(memmap[SIFIVE_E_MROM].base, reset_vec, sizeof(reset_vec)); 195eb637edbSMichael Clark memory_region_set_readonly(mask_rom, true); 196eb637edbSMichael Clark 197eb637edbSMichael Clark if (machine->kernel_filename) { 198eb637edbSMichael Clark load_kernel(machine->kernel_filename); 199eb637edbSMichael Clark } 200eb637edbSMichael Clark } 201eb637edbSMichael Clark 202eb637edbSMichael Clark static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev) 203eb637edbSMichael Clark { 204eb637edbSMichael Clark return 0; 205eb637edbSMichael Clark } 206eb637edbSMichael Clark 207eb637edbSMichael Clark static void riscv_sifive_e_class_init(ObjectClass *klass, void *data) 208eb637edbSMichael Clark { 209eb637edbSMichael Clark SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 210eb637edbSMichael Clark k->init = riscv_sifive_e_sysbus_device_init; 211eb637edbSMichael Clark } 212eb637edbSMichael Clark 213eb637edbSMichael Clark static const TypeInfo riscv_sifive_e_device = { 214eb637edbSMichael Clark .name = TYPE_SIFIVE_E, 215eb637edbSMichael Clark .parent = TYPE_SYS_BUS_DEVICE, 216eb637edbSMichael Clark .instance_size = sizeof(SiFiveEState), 217eb637edbSMichael Clark .class_init = riscv_sifive_e_class_init, 218eb637edbSMichael Clark }; 219eb637edbSMichael Clark 220eb637edbSMichael Clark static void riscv_sifive_e_machine_init(MachineClass *mc) 221eb637edbSMichael Clark { 222eb637edbSMichael Clark mc->desc = "RISC-V Board compatible with SiFive E SDK"; 223eb637edbSMichael Clark mc->init = riscv_sifive_e_init; 224eb637edbSMichael Clark mc->max_cpus = 1; 225eb637edbSMichael Clark } 226eb637edbSMichael Clark 227eb637edbSMichael Clark DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) 228eb637edbSMichael Clark 229eb637edbSMichael Clark static void riscv_sifive_e_register_types(void) 230eb637edbSMichael Clark { 231eb637edbSMichael Clark type_register_static(&riscv_sifive_e_device); 232eb637edbSMichael Clark } 233eb637edbSMichael Clark 234eb637edbSMichael Clark type_init(riscv_sifive_e_register_types); 235