1eb637edbSMichael Clark /* 2eb637edbSMichael Clark * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3eb637edbSMichael Clark * 4eb637edbSMichael Clark * Copyright (c) 2017 SiFive, Inc. 5eb637edbSMichael Clark * 6eb637edbSMichael Clark * Provides a board compatible with the SiFive Freedom E SDK: 7eb637edbSMichael Clark * 8eb637edbSMichael Clark * 0) UART 9eb637edbSMichael Clark * 1) CLINT (Core Level Interruptor) 10eb637edbSMichael Clark * 2) PLIC (Platform Level Interrupt Controller) 11eb637edbSMichael Clark * 3) PRCI (Power, Reset, Clock, Interrupt) 12eb637edbSMichael Clark * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13eb637edbSMichael Clark * 5) Flash memory emulated as RAM 14eb637edbSMichael Clark * 15eb637edbSMichael Clark * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16eb637edbSMichael Clark * The OTP ROM and Flash boot code will be emulated in a future version. 17eb637edbSMichael Clark * 18eb637edbSMichael Clark * This program is free software; you can redistribute it and/or modify it 19eb637edbSMichael Clark * under the terms and conditions of the GNU General Public License, 20eb637edbSMichael Clark * version 2 or later, as published by the Free Software Foundation. 21eb637edbSMichael Clark * 22eb637edbSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 23eb637edbSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24eb637edbSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25eb637edbSMichael Clark * more details. 26eb637edbSMichael Clark * 27eb637edbSMichael Clark * You should have received a copy of the GNU General Public License along with 28eb637edbSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 29eb637edbSMichael Clark */ 30eb637edbSMichael Clark 31eb637edbSMichael Clark #include "qemu/osdep.h" 32eb637edbSMichael Clark #include "qemu/log.h" 33eb637edbSMichael Clark #include "qemu/error-report.h" 34eb637edbSMichael Clark #include "qapi/error.h" 35eb637edbSMichael Clark #include "hw/boards.h" 36eb637edbSMichael Clark #include "hw/loader.h" 37eb637edbSMichael Clark #include "hw/sysbus.h" 38eb637edbSMichael Clark #include "hw/char/serial.h" 39eb637edbSMichael Clark #include "target/riscv/cpu.h" 40eb637edbSMichael Clark #include "hw/riscv/riscv_hart.h" 41eb637edbSMichael Clark #include "hw/riscv/sifive_plic.h" 42eb637edbSMichael Clark #include "hw/riscv/sifive_clint.h" 43eb637edbSMichael Clark #include "hw/riscv/sifive_uart.h" 44eb637edbSMichael Clark #include "hw/riscv/sifive_e.h" 45*56449d20SBin Meng #include "hw/riscv/sifive_e_prci.h" 460ac24d56SAlistair Francis #include "hw/riscv/boot.h" 47eb637edbSMichael Clark #include "chardev/char.h" 48eb637edbSMichael Clark #include "sysemu/arch_init.h" 4946517dd4SMarkus Armbruster #include "sysemu/sysemu.h" 50eb637edbSMichael Clark #include "exec/address-spaces.h" 51eb637edbSMichael Clark 52eb637edbSMichael Clark static const struct MemmapEntry { 53eb637edbSMichael Clark hwaddr base; 54eb637edbSMichael Clark hwaddr size; 55eb637edbSMichael Clark } sifive_e_memmap[] = { 56eb637edbSMichael Clark [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, 57eb637edbSMichael Clark [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, 58eb637edbSMichael Clark [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, 59eb637edbSMichael Clark [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, 60eb637edbSMichael Clark [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, 61eb637edbSMichael Clark [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, 62eb637edbSMichael Clark [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, 63eb637edbSMichael Clark [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, 64eb637edbSMichael Clark [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, 65eb637edbSMichael Clark [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, 66eb637edbSMichael Clark [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, 67eb637edbSMichael Clark [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, 68eb637edbSMichael Clark [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, 69eb637edbSMichael Clark [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, 70eb637edbSMichael Clark [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, 71eb637edbSMichael Clark [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, 72eb637edbSMichael Clark [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, 73eb637edbSMichael Clark [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, 74eb637edbSMichael Clark [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } 75eb637edbSMichael Clark }; 76eb637edbSMichael Clark 77eb637edbSMichael Clark static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, 78eb637edbSMichael Clark uintptr_t offset, uintptr_t length) 79eb637edbSMichael Clark { 80eb637edbSMichael Clark MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); 81eb637edbSMichael Clark memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); 82eb637edbSMichael Clark memory_region_add_subregion(parent, offset, mock_mmio); 83eb637edbSMichael Clark } 84eb637edbSMichael Clark 85eb637edbSMichael Clark static void riscv_sifive_e_init(MachineState *machine) 86eb637edbSMichael Clark { 87eb637edbSMichael Clark const struct MemmapEntry *memmap = sifive_e_memmap; 88eb637edbSMichael Clark 89eb637edbSMichael Clark SiFiveEState *s = g_new0(SiFiveEState, 1); 90eb637edbSMichael Clark MemoryRegion *sys_mem = get_system_memory(); 91eb637edbSMichael Clark MemoryRegion *main_mem = g_new(MemoryRegion, 1); 925aec3247SMichael Clark int i; 93eb637edbSMichael Clark 94651cd8b7SAlistair Francis /* Initialize SoC */ 9554f3141aSAlistair Francis object_initialize_child(OBJECT(machine), "soc", &s->soc, 9654f3141aSAlistair Francis sizeof(s->soc), TYPE_RISCV_E_SOC, 9754f3141aSAlistair Francis &error_abort, NULL); 98eb637edbSMichael Clark object_property_set_bool(OBJECT(&s->soc), true, "realized", 99eb637edbSMichael Clark &error_abort); 100eb637edbSMichael Clark 101eb637edbSMichael Clark /* Data Tightly Integrated Memory */ 102eb637edbSMichael Clark memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 103eb637edbSMichael Clark memmap[SIFIVE_E_DTIM].size, &error_fatal); 104eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 105eb637edbSMichael Clark memmap[SIFIVE_E_DTIM].base, main_mem); 106eb637edbSMichael Clark 107651cd8b7SAlistair Francis /* Mask ROM reset vector */ 108651cd8b7SAlistair Francis uint32_t reset_vec[2] = { 109651cd8b7SAlistair Francis 0x204002b7, /* 0x1000: lui t0,0x20400 */ 110651cd8b7SAlistair Francis 0x00028067, /* 0x1004: jr t0 */ 111651cd8b7SAlistair Francis }; 112651cd8b7SAlistair Francis 113651cd8b7SAlistair Francis /* copy in the reset vector in little_endian byte order */ 114651cd8b7SAlistair Francis for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 115651cd8b7SAlistair Francis reset_vec[i] = cpu_to_le32(reset_vec[i]); 116651cd8b7SAlistair Francis } 117651cd8b7SAlistair Francis rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 118651cd8b7SAlistair Francis memmap[SIFIVE_E_MROM].base, &address_space_memory); 119651cd8b7SAlistair Francis 120651cd8b7SAlistair Francis if (machine->kernel_filename) { 1210ac24d56SAlistair Francis riscv_load_kernel(machine->kernel_filename); 122651cd8b7SAlistair Francis } 123651cd8b7SAlistair Francis } 124651cd8b7SAlistair Francis 125651cd8b7SAlistair Francis static void riscv_sifive_e_soc_init(Object *obj) 126651cd8b7SAlistair Francis { 127c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 128651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(obj); 129651cd8b7SAlistair Francis 13054f3141aSAlistair Francis object_initialize_child(obj, "cpus", &s->cpus, 13154f3141aSAlistair Francis sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, 13254f3141aSAlistair Francis &error_abort, NULL); 133651cd8b7SAlistair Francis object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", 134651cd8b7SAlistair Francis &error_abort); 135c4473127SLike Xu object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 136651cd8b7SAlistair Francis &error_abort); 13730efbf33SFabien Chouteau sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", 13830efbf33SFabien Chouteau &s->gpio, sizeof(s->gpio), 13930efbf33SFabien Chouteau TYPE_SIFIVE_GPIO); 140651cd8b7SAlistair Francis } 141651cd8b7SAlistair Francis 142651cd8b7SAlistair Francis static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) 143651cd8b7SAlistair Francis { 144c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 145651cd8b7SAlistair Francis const struct MemmapEntry *memmap = sifive_e_memmap; 14630efbf33SFabien Chouteau Error *err = NULL; 147651cd8b7SAlistair Francis 148651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(dev); 149651cd8b7SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 150651cd8b7SAlistair Francis 151651cd8b7SAlistair Francis object_property_set_bool(OBJECT(&s->cpus), true, "realized", 152651cd8b7SAlistair Francis &error_abort); 153651cd8b7SAlistair Francis 154eb637edbSMichael Clark /* Mask ROM */ 155c988de41SPalmer Dabbelt memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom", 156eb637edbSMichael Clark memmap[SIFIVE_E_MROM].size, &error_fatal); 157eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 158c988de41SPalmer Dabbelt memmap[SIFIVE_E_MROM].base, &s->mask_rom); 159eb637edbSMichael Clark 160eb637edbSMichael Clark /* MMIO */ 161eb637edbSMichael Clark s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, 162eb637edbSMichael Clark (char *)SIFIVE_E_PLIC_HART_CONFIG, 163eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_SOURCES, 164eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_PRIORITIES, 165eb637edbSMichael Clark SIFIVE_E_PLIC_PRIORITY_BASE, 166eb637edbSMichael Clark SIFIVE_E_PLIC_PENDING_BASE, 167eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_BASE, 168eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_STRIDE, 169eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_BASE, 170eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_STRIDE, 171eb637edbSMichael Clark memmap[SIFIVE_E_PLIC].size); 172eb637edbSMichael Clark sifive_clint_create(memmap[SIFIVE_E_CLINT].base, 173c4473127SLike Xu memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, 174eb637edbSMichael Clark SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 175eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", 176eb637edbSMichael Clark memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); 177*56449d20SBin Meng sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); 17830efbf33SFabien Chouteau 17930efbf33SFabien Chouteau /* GPIO */ 18030efbf33SFabien Chouteau 18130efbf33SFabien Chouteau object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); 18230efbf33SFabien Chouteau if (err) { 18330efbf33SFabien Chouteau error_propagate(errp, err); 18430efbf33SFabien Chouteau return; 18530efbf33SFabien Chouteau } 18630efbf33SFabien Chouteau 18730efbf33SFabien Chouteau /* Map GPIO registers */ 18830efbf33SFabien Chouteau sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base); 18930efbf33SFabien Chouteau 19030efbf33SFabien Chouteau /* Pass all GPIOs to the SOC layer so they are available to the board */ 19130efbf33SFabien Chouteau qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 19230efbf33SFabien Chouteau 19330efbf33SFabien Chouteau /* Connect GPIO interrupts to the PLIC */ 19430efbf33SFabien Chouteau for (int i = 0; i < 32; i++) { 19530efbf33SFabien Chouteau sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 19630efbf33SFabien Chouteau qdev_get_gpio_in(DEVICE(s->plic), 19730efbf33SFabien Chouteau SIFIVE_E_GPIO0_IRQ0 + i)); 19830efbf33SFabien Chouteau } 19930efbf33SFabien Chouteau 200eb637edbSMichael Clark sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, 201647a70a1SAlistair Francis serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 202eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", 203eb637edbSMichael Clark memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); 204eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", 205eb637edbSMichael Clark memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); 206194eef09SMichael Clark sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, 207194eef09SMichael Clark serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 208eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", 209eb637edbSMichael Clark memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); 210eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", 211eb637edbSMichael Clark memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); 212eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", 213eb637edbSMichael Clark memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); 214eb637edbSMichael Clark sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", 215eb637edbSMichael Clark memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); 216eb637edbSMichael Clark 217eb637edbSMichael Clark /* Flash memory */ 218c988de41SPalmer Dabbelt memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip", 219eb637edbSMichael Clark memmap[SIFIVE_E_XIP].size, &error_fatal); 220c988de41SPalmer Dabbelt memory_region_set_readonly(&s->xip_mem, true); 221c988de41SPalmer Dabbelt memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, 222c988de41SPalmer Dabbelt &s->xip_mem); 223eb637edbSMichael Clark } 224eb637edbSMichael Clark 225eb637edbSMichael Clark static void riscv_sifive_e_machine_init(MachineClass *mc) 226eb637edbSMichael Clark { 227eb637edbSMichael Clark mc->desc = "RISC-V Board compatible with SiFive E SDK"; 228eb637edbSMichael Clark mc->init = riscv_sifive_e_init; 229eb637edbSMichael Clark mc->max_cpus = 1; 230eb637edbSMichael Clark } 231eb637edbSMichael Clark 232eb637edbSMichael Clark DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) 233651cd8b7SAlistair Francis 234651cd8b7SAlistair Francis static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) 235651cd8b7SAlistair Francis { 236651cd8b7SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc); 237651cd8b7SAlistair Francis 238651cd8b7SAlistair Francis dc->realize = riscv_sifive_e_soc_realize; 239651cd8b7SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 240651cd8b7SAlistair Francis dc->user_creatable = false; 241651cd8b7SAlistair Francis } 242651cd8b7SAlistair Francis 243651cd8b7SAlistair Francis static const TypeInfo riscv_sifive_e_soc_type_info = { 244651cd8b7SAlistair Francis .name = TYPE_RISCV_E_SOC, 245651cd8b7SAlistair Francis .parent = TYPE_DEVICE, 246651cd8b7SAlistair Francis .instance_size = sizeof(SiFiveESoCState), 247651cd8b7SAlistair Francis .instance_init = riscv_sifive_e_soc_init, 248651cd8b7SAlistair Francis .class_init = riscv_sifive_e_soc_class_init, 249651cd8b7SAlistair Francis }; 250651cd8b7SAlistair Francis 251651cd8b7SAlistair Francis static void riscv_sifive_e_soc_register_types(void) 252651cd8b7SAlistair Francis { 253651cd8b7SAlistair Francis type_register_static(&riscv_sifive_e_soc_type_info); 254651cd8b7SAlistair Francis } 255651cd8b7SAlistair Francis 256651cd8b7SAlistair Francis type_init(riscv_sifive_e_soc_register_types) 257