1eb637edbSMichael Clark /* 2eb637edbSMichael Clark * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3eb637edbSMichael Clark * 4eb637edbSMichael Clark * Copyright (c) 2017 SiFive, Inc. 5eb637edbSMichael Clark * 6eb637edbSMichael Clark * Provides a board compatible with the SiFive Freedom E SDK: 7eb637edbSMichael Clark * 8eb637edbSMichael Clark * 0) UART 9eb637edbSMichael Clark * 1) CLINT (Core Level Interruptor) 10eb637edbSMichael Clark * 2) PLIC (Platform Level Interrupt Controller) 11eb637edbSMichael Clark * 3) PRCI (Power, Reset, Clock, Interrupt) 12eb637edbSMichael Clark * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13eb637edbSMichael Clark * 5) Flash memory emulated as RAM 14eb637edbSMichael Clark * 15eb637edbSMichael Clark * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16eb637edbSMichael Clark * The OTP ROM and Flash boot code will be emulated in a future version. 17eb637edbSMichael Clark * 18eb637edbSMichael Clark * This program is free software; you can redistribute it and/or modify it 19eb637edbSMichael Clark * under the terms and conditions of the GNU General Public License, 20eb637edbSMichael Clark * version 2 or later, as published by the Free Software Foundation. 21eb637edbSMichael Clark * 22eb637edbSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 23eb637edbSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24eb637edbSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25eb637edbSMichael Clark * more details. 26eb637edbSMichael Clark * 27eb637edbSMichael Clark * You should have received a copy of the GNU General Public License along with 28eb637edbSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 29eb637edbSMichael Clark */ 30eb637edbSMichael Clark 31eb637edbSMichael Clark #include "qemu/osdep.h" 32eb637edbSMichael Clark #include "qemu/error-report.h" 33eb637edbSMichael Clark #include "qapi/error.h" 34eb637edbSMichael Clark #include "hw/boards.h" 35eb637edbSMichael Clark #include "hw/loader.h" 36eb637edbSMichael Clark #include "hw/sysbus.h" 37eb637edbSMichael Clark #include "hw/char/serial.h" 3868c9a9b3SBin Meng #include "hw/misc/unimp.h" 39eb637edbSMichael Clark #include "target/riscv/cpu.h" 40eb637edbSMichael Clark #include "hw/riscv/riscv_hart.h" 41eb637edbSMichael Clark #include "hw/riscv/sifive_e.h" 420ac24d56SAlistair Francis #include "hw/riscv/boot.h" 43b609b7e3SBin Meng #include "hw/char/sifive_uart.h" 44406fafd5SBin Meng #include "hw/intc/sifive_clint.h" 4584fcf3c1SBin Meng #include "hw/intc/sifive_plic.h" 4689ece6f7SBin Meng #include "hw/misc/sifive_e_prci.h" 47eb637edbSMichael Clark #include "chardev/char.h" 48eb637edbSMichael Clark #include "sysemu/arch_init.h" 4946517dd4SMarkus Armbruster #include "sysemu/sysemu.h" 50eb637edbSMichael Clark 51*3de70cecSBin Meng static const MemMapEntry sifive_e_memmap[] = { 525488f276SEduardo Habkost [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 }, 535488f276SEduardo Habkost [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 }, 545488f276SEduardo Habkost [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 }, 555488f276SEduardo Habkost [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 }, 565488f276SEduardo Habkost [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 }, 575488f276SEduardo Habkost [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 }, 585488f276SEduardo Habkost [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 }, 595488f276SEduardo Habkost [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 }, 605488f276SEduardo Habkost [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 }, 615488f276SEduardo Habkost [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 }, 625488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 }, 635488f276SEduardo Habkost [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 }, 645488f276SEduardo Habkost [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 }, 655488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 }, 665488f276SEduardo Habkost [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 }, 675488f276SEduardo Habkost [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 }, 685488f276SEduardo Habkost [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 }, 695488f276SEduardo Habkost [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 }, 705488f276SEduardo Habkost [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 } 71eb637edbSMichael Clark }; 72eb637edbSMichael Clark 738f8c6c1aSBin Meng static void sifive_e_machine_init(MachineState *machine) 74eb637edbSMichael Clark { 7573261285SBin Meng const MemMapEntry *memmap = sifive_e_memmap; 76eb637edbSMichael Clark 770869490bSAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(machine); 78eb637edbSMichael Clark MemoryRegion *sys_mem = get_system_memory(); 79eb637edbSMichael Clark MemoryRegion *main_mem = g_new(MemoryRegion, 1); 805aec3247SMichael Clark int i; 81eb637edbSMichael Clark 82651cd8b7SAlistair Francis /* Initialize SoC */ 839fc7fc4dSMarkus Armbruster object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); 84ce189ab2SMarkus Armbruster qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 85eb637edbSMichael Clark 86eb637edbSMichael Clark /* Data Tightly Integrated Memory */ 87eb637edbSMichael Clark memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 885488f276SEduardo Habkost memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal); 89eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 905488f276SEduardo Habkost memmap[SIFIVE_E_DEV_DTIM].base, main_mem); 91eb637edbSMichael Clark 92651cd8b7SAlistair Francis /* Mask ROM reset vector */ 93495134b7SBin Meng uint32_t reset_vec[4]; 945a842062SAlistair Francis 955a842062SAlistair Francis if (s->revb) { 96495134b7SBin Meng reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ 975a842062SAlistair Francis } else { 98495134b7SBin Meng reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ 995a842062SAlistair Francis } 100495134b7SBin Meng reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ 101495134b7SBin Meng 102495134b7SBin Meng reset_vec[0] = reset_vec[3] = 0; 103651cd8b7SAlistair Francis 104651cd8b7SAlistair Francis /* copy in the reset vector in little_endian byte order */ 105651cd8b7SAlistair Francis for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 106651cd8b7SAlistair Francis reset_vec[i] = cpu_to_le32(reset_vec[i]); 107651cd8b7SAlistair Francis } 108651cd8b7SAlistair Francis rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 1095488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); 110651cd8b7SAlistair Francis 111651cd8b7SAlistair Francis if (machine->kernel_filename) { 11238bc4e34SAlistair Francis riscv_load_kernel(machine->kernel_filename, 11338bc4e34SAlistair Francis memmap[SIFIVE_E_DEV_DTIM].base, NULL); 114651cd8b7SAlistair Francis } 115651cd8b7SAlistair Francis } 116651cd8b7SAlistair Francis 1175a842062SAlistair Francis static bool sifive_e_machine_get_revb(Object *obj, Error **errp) 1185a842062SAlistair Francis { 1195a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1205a842062SAlistair Francis 1215a842062SAlistair Francis return s->revb; 1225a842062SAlistair Francis } 1235a842062SAlistair Francis 1245a842062SAlistair Francis static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp) 1255a842062SAlistair Francis { 1265a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1275a842062SAlistair Francis 1285a842062SAlistair Francis s->revb = value; 1295a842062SAlistair Francis } 1305a842062SAlistair Francis 1310869490bSAlistair Francis static void sifive_e_machine_instance_init(Object *obj) 1320869490bSAlistair Francis { 1335a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1345a842062SAlistair Francis 1355a842062SAlistair Francis s->revb = false; 1360869490bSAlistair Francis } 1370869490bSAlistair Francis 1380869490bSAlistair Francis static void sifive_e_machine_class_init(ObjectClass *oc, void *data) 1390869490bSAlistair Francis { 1400869490bSAlistair Francis MachineClass *mc = MACHINE_CLASS(oc); 1410869490bSAlistair Francis 1420869490bSAlistair Francis mc->desc = "RISC-V Board compatible with SiFive E SDK"; 1438f8c6c1aSBin Meng mc->init = sifive_e_machine_init; 1440869490bSAlistair Francis mc->max_cpus = 1; 1450869490bSAlistair Francis mc->default_cpu_type = SIFIVE_E_CPU; 146fabbcbd9SEduardo Habkost 147fabbcbd9SEduardo Habkost object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb, 148fabbcbd9SEduardo Habkost sifive_e_machine_set_revb); 149fabbcbd9SEduardo Habkost object_class_property_set_description(oc, "revb", 150fabbcbd9SEduardo Habkost "Set on to tell QEMU that it should model " 151fabbcbd9SEduardo Habkost "the revB HiFive1 board"); 1520869490bSAlistair Francis } 1530869490bSAlistair Francis 1540869490bSAlistair Francis static const TypeInfo sifive_e_machine_typeinfo = { 1550869490bSAlistair Francis .name = MACHINE_TYPE_NAME("sifive_e"), 1560869490bSAlistair Francis .parent = TYPE_MACHINE, 1570869490bSAlistair Francis .class_init = sifive_e_machine_class_init, 1580869490bSAlistair Francis .instance_init = sifive_e_machine_instance_init, 1590869490bSAlistair Francis .instance_size = sizeof(SiFiveEState), 1600869490bSAlistair Francis }; 1610869490bSAlistair Francis 1620869490bSAlistair Francis static void sifive_e_machine_init_register_types(void) 1630869490bSAlistair Francis { 1640869490bSAlistair Francis type_register_static(&sifive_e_machine_typeinfo); 1650869490bSAlistair Francis } 1660869490bSAlistair Francis 1670869490bSAlistair Francis type_init(sifive_e_machine_init_register_types) 1680869490bSAlistair Francis 1698f8c6c1aSBin Meng static void sifive_e_soc_init(Object *obj) 170651cd8b7SAlistair Francis { 171c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 172651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(obj); 173651cd8b7SAlistair Francis 174db873cc5SMarkus Armbruster object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 1755325cc34SMarkus Armbruster object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 176651cd8b7SAlistair Francis &error_abort); 17773f6ed97SBin Meng object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); 178db873cc5SMarkus Armbruster object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, 17930efbf33SFabien Chouteau TYPE_SIFIVE_GPIO); 180651cd8b7SAlistair Francis } 181651cd8b7SAlistair Francis 1828f8c6c1aSBin Meng static void sifive_e_soc_realize(DeviceState *dev, Error **errp) 183651cd8b7SAlistair Francis { 184c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 18573261285SBin Meng const MemMapEntry *memmap = sifive_e_memmap; 186651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(dev); 187651cd8b7SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 188651cd8b7SAlistair Francis 1895325cc34SMarkus Armbruster object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 19074dbba9bSCorey Wharton &error_abort); 191db873cc5SMarkus Armbruster sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 192651cd8b7SAlistair Francis 193eb637edbSMichael Clark /* Mask ROM */ 194414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", 1955488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); 196eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 1975488f276SEduardo Habkost memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); 198eb637edbSMichael Clark 199eb637edbSMichael Clark /* MMIO */ 2005488f276SEduardo Habkost s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, 201c9270e10SAnup Patel (char *)SIFIVE_E_PLIC_HART_CONFIG, 0, 202eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_SOURCES, 203eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_PRIORITIES, 204eb637edbSMichael Clark SIFIVE_E_PLIC_PRIORITY_BASE, 205eb637edbSMichael Clark SIFIVE_E_PLIC_PENDING_BASE, 206eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_BASE, 207eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_STRIDE, 208eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_BASE, 209eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_STRIDE, 2105488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PLIC].size); 2115488f276SEduardo Habkost sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base, 2125488f276SEduardo Habkost memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus, 213a47ef6e9SBin Meng SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 214a47ef6e9SBin Meng SIFIVE_CLINT_TIMEBASE_FREQ, false); 21568c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.aon", 2165488f276SEduardo Habkost memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); 2175488f276SEduardo Habkost sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); 21830efbf33SFabien Chouteau 21930efbf33SFabien Chouteau /* GPIO */ 22030efbf33SFabien Chouteau 221668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 22230efbf33SFabien Chouteau return; 22330efbf33SFabien Chouteau } 22430efbf33SFabien Chouteau 22530efbf33SFabien Chouteau /* Map GPIO registers */ 2265488f276SEduardo Habkost sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base); 22730efbf33SFabien Chouteau 22830efbf33SFabien Chouteau /* Pass all GPIOs to the SOC layer so they are available to the board */ 22930efbf33SFabien Chouteau qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 23030efbf33SFabien Chouteau 23130efbf33SFabien Chouteau /* Connect GPIO interrupts to the PLIC */ 23230efbf33SFabien Chouteau for (int i = 0; i < 32; i++) { 23330efbf33SFabien Chouteau sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 23430efbf33SFabien Chouteau qdev_get_gpio_in(DEVICE(s->plic), 23530efbf33SFabien Chouteau SIFIVE_E_GPIO0_IRQ0 + i)); 23630efbf33SFabien Chouteau } 23730efbf33SFabien Chouteau 2385488f276SEduardo Habkost sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, 239647a70a1SAlistair Francis serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 24068c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi0", 2415488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); 24268c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm0", 2435488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); 2445488f276SEduardo Habkost sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, 245194eef09SMichael Clark serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 24668c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi1", 2475488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); 24868c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm1", 2495488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); 25068c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi2", 2515488f276SEduardo Habkost memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); 25268c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm2", 2535488f276SEduardo Habkost memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size); 254eb637edbSMichael Clark 255eb637edbSMichael Clark /* Flash memory */ 256414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", 2575488f276SEduardo Habkost memmap[SIFIVE_E_DEV_XIP].size, &error_fatal); 2585488f276SEduardo Habkost memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base, 259c988de41SPalmer Dabbelt &s->xip_mem); 260eb637edbSMichael Clark } 261eb637edbSMichael Clark 2628f8c6c1aSBin Meng static void sifive_e_soc_class_init(ObjectClass *oc, void *data) 263651cd8b7SAlistair Francis { 264651cd8b7SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc); 265651cd8b7SAlistair Francis 2668f8c6c1aSBin Meng dc->realize = sifive_e_soc_realize; 267651cd8b7SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 268651cd8b7SAlistair Francis dc->user_creatable = false; 269651cd8b7SAlistair Francis } 270651cd8b7SAlistair Francis 2718f8c6c1aSBin Meng static const TypeInfo sifive_e_soc_type_info = { 272651cd8b7SAlistair Francis .name = TYPE_RISCV_E_SOC, 273651cd8b7SAlistair Francis .parent = TYPE_DEVICE, 274651cd8b7SAlistair Francis .instance_size = sizeof(SiFiveESoCState), 2758f8c6c1aSBin Meng .instance_init = sifive_e_soc_init, 2768f8c6c1aSBin Meng .class_init = sifive_e_soc_class_init, 277651cd8b7SAlistair Francis }; 278651cd8b7SAlistair Francis 2798f8c6c1aSBin Meng static void sifive_e_soc_register_types(void) 280651cd8b7SAlistair Francis { 2818f8c6c1aSBin Meng type_register_static(&sifive_e_soc_type_info); 282651cd8b7SAlistair Francis } 283651cd8b7SAlistair Francis 2848f8c6c1aSBin Meng type_init(sifive_e_soc_register_types) 285