1eb637edbSMichael Clark /* 2eb637edbSMichael Clark * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3eb637edbSMichael Clark * 4eb637edbSMichael Clark * Copyright (c) 2017 SiFive, Inc. 5eb637edbSMichael Clark * 6eb637edbSMichael Clark * Provides a board compatible with the SiFive Freedom E SDK: 7eb637edbSMichael Clark * 8eb637edbSMichael Clark * 0) UART 9eb637edbSMichael Clark * 1) CLINT (Core Level Interruptor) 10eb637edbSMichael Clark * 2) PLIC (Platform Level Interrupt Controller) 11eb637edbSMichael Clark * 3) PRCI (Power, Reset, Clock, Interrupt) 12eb637edbSMichael Clark * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13eb637edbSMichael Clark * 5) Flash memory emulated as RAM 14eb637edbSMichael Clark * 15eb637edbSMichael Clark * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16eb637edbSMichael Clark * The OTP ROM and Flash boot code will be emulated in a future version. 17eb637edbSMichael Clark * 18eb637edbSMichael Clark * This program is free software; you can redistribute it and/or modify it 19eb637edbSMichael Clark * under the terms and conditions of the GNU General Public License, 20eb637edbSMichael Clark * version 2 or later, as published by the Free Software Foundation. 21eb637edbSMichael Clark * 22eb637edbSMichael Clark * This program is distributed in the hope it will be useful, but WITHOUT 23eb637edbSMichael Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24eb637edbSMichael Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25eb637edbSMichael Clark * more details. 26eb637edbSMichael Clark * 27eb637edbSMichael Clark * You should have received a copy of the GNU General Public License along with 28eb637edbSMichael Clark * this program. If not, see <http://www.gnu.org/licenses/>. 29eb637edbSMichael Clark */ 30eb637edbSMichael Clark 31eb637edbSMichael Clark #include "qemu/osdep.h" 32eb637edbSMichael Clark #include "qemu/log.h" 33eb637edbSMichael Clark #include "qemu/error-report.h" 34eb637edbSMichael Clark #include "qapi/error.h" 35eb637edbSMichael Clark #include "hw/boards.h" 36eb637edbSMichael Clark #include "hw/loader.h" 37eb637edbSMichael Clark #include "hw/sysbus.h" 38eb637edbSMichael Clark #include "hw/char/serial.h" 3968c9a9b3SBin Meng #include "hw/misc/unimp.h" 40eb637edbSMichael Clark #include "target/riscv/cpu.h" 41eb637edbSMichael Clark #include "hw/riscv/riscv_hart.h" 42eb637edbSMichael Clark #include "hw/riscv/sifive_plic.h" 43eb637edbSMichael Clark #include "hw/riscv/sifive_clint.h" 44eb637edbSMichael Clark #include "hw/riscv/sifive_uart.h" 45eb637edbSMichael Clark #include "hw/riscv/sifive_e.h" 4656449d20SBin Meng #include "hw/riscv/sifive_e_prci.h" 470ac24d56SAlistair Francis #include "hw/riscv/boot.h" 48eb637edbSMichael Clark #include "chardev/char.h" 49eb637edbSMichael Clark #include "sysemu/arch_init.h" 5046517dd4SMarkus Armbruster #include "sysemu/sysemu.h" 51eb637edbSMichael Clark #include "exec/address-spaces.h" 52eb637edbSMichael Clark 53eb637edbSMichael Clark static const struct MemmapEntry { 54eb637edbSMichael Clark hwaddr base; 55eb637edbSMichael Clark hwaddr size; 56eb637edbSMichael Clark } sifive_e_memmap[] = { 57e79d27cbSBin Meng [SIFIVE_E_DEBUG] = { 0x0, 0x1000 }, 58eb637edbSMichael Clark [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, 59eb637edbSMichael Clark [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, 60eb637edbSMichael Clark [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, 61eb637edbSMichael Clark [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, 62eb637edbSMichael Clark [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, 63eb637edbSMichael Clark [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, 64eb637edbSMichael Clark [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, 65eb637edbSMichael Clark [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, 66eb637edbSMichael Clark [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, 67eb637edbSMichael Clark [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, 68eb637edbSMichael Clark [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, 69eb637edbSMichael Clark [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, 70eb637edbSMichael Clark [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, 71eb637edbSMichael Clark [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, 72eb637edbSMichael Clark [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, 73eb637edbSMichael Clark [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, 74eb637edbSMichael Clark [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, 75eb637edbSMichael Clark [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } 76eb637edbSMichael Clark }; 77eb637edbSMichael Clark 788f8c6c1aSBin Meng static void sifive_e_machine_init(MachineState *machine) 79eb637edbSMichael Clark { 80eb637edbSMichael Clark const struct MemmapEntry *memmap = sifive_e_memmap; 81eb637edbSMichael Clark 820869490bSAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(machine); 83eb637edbSMichael Clark MemoryRegion *sys_mem = get_system_memory(); 84eb637edbSMichael Clark MemoryRegion *main_mem = g_new(MemoryRegion, 1); 855aec3247SMichael Clark int i; 86eb637edbSMichael Clark 87651cd8b7SAlistair Francis /* Initialize SoC */ 889fc7fc4dSMarkus Armbruster object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); 89ce189ab2SMarkus Armbruster qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 90eb637edbSMichael Clark 91eb637edbSMichael Clark /* Data Tightly Integrated Memory */ 92eb637edbSMichael Clark memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 93eb637edbSMichael Clark memmap[SIFIVE_E_DTIM].size, &error_fatal); 94eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 95eb637edbSMichael Clark memmap[SIFIVE_E_DTIM].base, main_mem); 96eb637edbSMichael Clark 97651cd8b7SAlistair Francis /* Mask ROM reset vector */ 98495134b7SBin Meng uint32_t reset_vec[4]; 995a842062SAlistair Francis 1005a842062SAlistair Francis if (s->revb) { 101495134b7SBin Meng reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ 1025a842062SAlistair Francis } else { 103495134b7SBin Meng reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ 1045a842062SAlistair Francis } 105495134b7SBin Meng reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ 106495134b7SBin Meng 107495134b7SBin Meng reset_vec[0] = reset_vec[3] = 0; 108651cd8b7SAlistair Francis 109651cd8b7SAlistair Francis /* copy in the reset vector in little_endian byte order */ 110651cd8b7SAlistair Francis for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 111651cd8b7SAlistair Francis reset_vec[i] = cpu_to_le32(reset_vec[i]); 112651cd8b7SAlistair Francis } 113651cd8b7SAlistair Francis rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 114651cd8b7SAlistair Francis memmap[SIFIVE_E_MROM].base, &address_space_memory); 115651cd8b7SAlistair Francis 116651cd8b7SAlistair Francis if (machine->kernel_filename) { 1176478dd74SZhuang, Siwei (Data61, Kensington NSW) riscv_load_kernel(machine->kernel_filename, NULL); 118651cd8b7SAlistair Francis } 119651cd8b7SAlistair Francis } 120651cd8b7SAlistair Francis 1215a842062SAlistair Francis static bool sifive_e_machine_get_revb(Object *obj, Error **errp) 1225a842062SAlistair Francis { 1235a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1245a842062SAlistair Francis 1255a842062SAlistair Francis return s->revb; 1265a842062SAlistair Francis } 1275a842062SAlistair Francis 1285a842062SAlistair Francis static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp) 1295a842062SAlistair Francis { 1305a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1315a842062SAlistair Francis 1325a842062SAlistair Francis s->revb = value; 1335a842062SAlistair Francis } 1345a842062SAlistair Francis 1350869490bSAlistair Francis static void sifive_e_machine_instance_init(Object *obj) 1360869490bSAlistair Francis { 1375a842062SAlistair Francis SiFiveEState *s = RISCV_E_MACHINE(obj); 1385a842062SAlistair Francis 1395a842062SAlistair Francis s->revb = false; 1405a842062SAlistair Francis object_property_add_bool(obj, "revb", sifive_e_machine_get_revb, 1415a842062SAlistair Francis sifive_e_machine_set_revb); 1425a842062SAlistair Francis object_property_set_description(obj, "revb", 1435a842062SAlistair Francis "Set on to tell QEMU that it should model " 1445a842062SAlistair Francis "the revB HiFive1 board"); 1450869490bSAlistair Francis } 1460869490bSAlistair Francis 1470869490bSAlistair Francis static void sifive_e_machine_class_init(ObjectClass *oc, void *data) 1480869490bSAlistair Francis { 1490869490bSAlistair Francis MachineClass *mc = MACHINE_CLASS(oc); 1500869490bSAlistair Francis 1510869490bSAlistair Francis mc->desc = "RISC-V Board compatible with SiFive E SDK"; 1528f8c6c1aSBin Meng mc->init = sifive_e_machine_init; 1530869490bSAlistair Francis mc->max_cpus = 1; 1540869490bSAlistair Francis mc->default_cpu_type = SIFIVE_E_CPU; 1550869490bSAlistair Francis } 1560869490bSAlistair Francis 1570869490bSAlistair Francis static const TypeInfo sifive_e_machine_typeinfo = { 1580869490bSAlistair Francis .name = MACHINE_TYPE_NAME("sifive_e"), 1590869490bSAlistair Francis .parent = TYPE_MACHINE, 1600869490bSAlistair Francis .class_init = sifive_e_machine_class_init, 1610869490bSAlistair Francis .instance_init = sifive_e_machine_instance_init, 1620869490bSAlistair Francis .instance_size = sizeof(SiFiveEState), 1630869490bSAlistair Francis }; 1640869490bSAlistair Francis 1650869490bSAlistair Francis static void sifive_e_machine_init_register_types(void) 1660869490bSAlistair Francis { 1670869490bSAlistair Francis type_register_static(&sifive_e_machine_typeinfo); 1680869490bSAlistair Francis } 1690869490bSAlistair Francis 1700869490bSAlistair Francis type_init(sifive_e_machine_init_register_types) 1710869490bSAlistair Francis 1728f8c6c1aSBin Meng static void sifive_e_soc_init(Object *obj) 173651cd8b7SAlistair Francis { 174c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 175651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(obj); 176651cd8b7SAlistair Francis 177db873cc5SMarkus Armbruster object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 1785325cc34SMarkus Armbruster object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 179651cd8b7SAlistair Francis &error_abort); 180db873cc5SMarkus Armbruster object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, 18130efbf33SFabien Chouteau TYPE_SIFIVE_GPIO); 182651cd8b7SAlistair Francis } 183651cd8b7SAlistair Francis 1848f8c6c1aSBin Meng static void sifive_e_soc_realize(DeviceState *dev, Error **errp) 185651cd8b7SAlistair Francis { 186c4473127SLike Xu MachineState *ms = MACHINE(qdev_get_machine()); 187651cd8b7SAlistair Francis const struct MemmapEntry *memmap = sifive_e_memmap; 188651cd8b7SAlistair Francis SiFiveESoCState *s = RISCV_E_SOC(dev); 189651cd8b7SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 190651cd8b7SAlistair Francis 1915325cc34SMarkus Armbruster object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 19274dbba9bSCorey Wharton &error_abort); 193db873cc5SMarkus Armbruster sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 194651cd8b7SAlistair Francis 195eb637edbSMichael Clark /* Mask ROM */ 196414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", 197eb637edbSMichael Clark memmap[SIFIVE_E_MROM].size, &error_fatal); 198eb637edbSMichael Clark memory_region_add_subregion(sys_mem, 199c988de41SPalmer Dabbelt memmap[SIFIVE_E_MROM].base, &s->mask_rom); 200eb637edbSMichael Clark 201eb637edbSMichael Clark /* MMIO */ 202eb637edbSMichael Clark s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, 203eb637edbSMichael Clark (char *)SIFIVE_E_PLIC_HART_CONFIG, 204eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_SOURCES, 205eb637edbSMichael Clark SIFIVE_E_PLIC_NUM_PRIORITIES, 206eb637edbSMichael Clark SIFIVE_E_PLIC_PRIORITY_BASE, 207eb637edbSMichael Clark SIFIVE_E_PLIC_PENDING_BASE, 208eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_BASE, 209eb637edbSMichael Clark SIFIVE_E_PLIC_ENABLE_STRIDE, 210eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_BASE, 211eb637edbSMichael Clark SIFIVE_E_PLIC_CONTEXT_STRIDE, 212eb637edbSMichael Clark memmap[SIFIVE_E_PLIC].size); 213eb637edbSMichael Clark sifive_clint_create(memmap[SIFIVE_E_CLINT].base, 214*3bf03f08SAnup Patel memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus, 2155f3616ccSAnup Patel SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); 21668c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.aon", 217eb637edbSMichael Clark memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); 21856449d20SBin Meng sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); 21930efbf33SFabien Chouteau 22030efbf33SFabien Chouteau /* GPIO */ 22130efbf33SFabien Chouteau 222668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 22330efbf33SFabien Chouteau return; 22430efbf33SFabien Chouteau } 22530efbf33SFabien Chouteau 22630efbf33SFabien Chouteau /* Map GPIO registers */ 22730efbf33SFabien Chouteau sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base); 22830efbf33SFabien Chouteau 22930efbf33SFabien Chouteau /* Pass all GPIOs to the SOC layer so they are available to the board */ 23030efbf33SFabien Chouteau qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 23130efbf33SFabien Chouteau 23230efbf33SFabien Chouteau /* Connect GPIO interrupts to the PLIC */ 23330efbf33SFabien Chouteau for (int i = 0; i < 32; i++) { 23430efbf33SFabien Chouteau sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 23530efbf33SFabien Chouteau qdev_get_gpio_in(DEVICE(s->plic), 23630efbf33SFabien Chouteau SIFIVE_E_GPIO0_IRQ0 + i)); 23730efbf33SFabien Chouteau } 23830efbf33SFabien Chouteau 239eb637edbSMichael Clark sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, 240647a70a1SAlistair Francis serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 24168c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi0", 242eb637edbSMichael Clark memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); 24368c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm0", 244eb637edbSMichael Clark memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); 245194eef09SMichael Clark sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, 246194eef09SMichael Clark serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 24768c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi1", 248eb637edbSMichael Clark memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); 24968c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm1", 250eb637edbSMichael Clark memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); 25168c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.qspi2", 252eb637edbSMichael Clark memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); 25368c9a9b3SBin Meng create_unimplemented_device("riscv.sifive.e.pwm2", 254eb637edbSMichael Clark memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); 255eb637edbSMichael Clark 256eb637edbSMichael Clark /* Flash memory */ 257414c47d2SPhilippe Mathieu-Daudé memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", 258eb637edbSMichael Clark memmap[SIFIVE_E_XIP].size, &error_fatal); 259c988de41SPalmer Dabbelt memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, 260c988de41SPalmer Dabbelt &s->xip_mem); 261eb637edbSMichael Clark } 262eb637edbSMichael Clark 2638f8c6c1aSBin Meng static void sifive_e_soc_class_init(ObjectClass *oc, void *data) 264651cd8b7SAlistair Francis { 265651cd8b7SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc); 266651cd8b7SAlistair Francis 2678f8c6c1aSBin Meng dc->realize = sifive_e_soc_realize; 268651cd8b7SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 269651cd8b7SAlistair Francis dc->user_creatable = false; 270651cd8b7SAlistair Francis } 271651cd8b7SAlistair Francis 2728f8c6c1aSBin Meng static const TypeInfo sifive_e_soc_type_info = { 273651cd8b7SAlistair Francis .name = TYPE_RISCV_E_SOC, 274651cd8b7SAlistair Francis .parent = TYPE_DEVICE, 275651cd8b7SAlistair Francis .instance_size = sizeof(SiFiveESoCState), 2768f8c6c1aSBin Meng .instance_init = sifive_e_soc_init, 2778f8c6c1aSBin Meng .class_init = sifive_e_soc_class_init, 278651cd8b7SAlistair Francis }; 279651cd8b7SAlistair Francis 2808f8c6c1aSBin Meng static void sifive_e_soc_register_types(void) 281651cd8b7SAlistair Francis { 2828f8c6c1aSBin Meng type_register_static(&sifive_e_soc_type_info); 283651cd8b7SAlistair Francis } 284651cd8b7SAlistair Francis 2858f8c6c1aSBin Meng type_init(sifive_e_soc_register_types) 286