1 /* 2 * QEMU RISCV Hart Array 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Holds the state of a homogeneous array of RISC-V harts 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/module.h" 24 #include "sysemu/reset.h" 25 #include "hw/sysbus.h" 26 #include "target/riscv/cpu.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/riscv/riscv_hart.h" 29 30 static Property riscv_harts_props[] = { 31 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), 32 DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), 33 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), 34 DEFINE_PROP_END_OF_LIST(), 35 }; 36 37 static void riscv_harts_cpu_reset(void *opaque) 38 { 39 RISCVCPU *cpu = opaque; 40 cpu_reset(CPU(cpu)); 41 } 42 43 static void riscv_hart_realize(RISCVHartArrayState *s, int idx, 44 char *cpu_type, Error **errp) 45 { 46 Error *err = NULL; 47 48 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); 49 s->harts[idx].env.mhartid = s->hartid_base + idx; 50 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); 51 qdev_realize(DEVICE(&s->harts[idx]), NULL, &err); 52 if (err) { 53 error_propagate(errp, err); 54 return; 55 } 56 } 57 58 static void riscv_harts_realize(DeviceState *dev, Error **errp) 59 { 60 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); 61 int n; 62 63 s->harts = g_new0(RISCVCPU, s->num_harts); 64 65 for (n = 0; n < s->num_harts; n++) { 66 riscv_hart_realize(s, n, s->cpu_type, errp); 67 } 68 } 69 70 static void riscv_harts_class_init(ObjectClass *klass, void *data) 71 { 72 DeviceClass *dc = DEVICE_CLASS(klass); 73 74 device_class_set_props(dc, riscv_harts_props); 75 dc->realize = riscv_harts_realize; 76 } 77 78 static const TypeInfo riscv_harts_info = { 79 .name = TYPE_RISCV_HART_ARRAY, 80 .parent = TYPE_SYS_BUS_DEVICE, 81 .instance_size = sizeof(RISCVHartArrayState), 82 .class_init = riscv_harts_class_init, 83 }; 84 85 static void riscv_harts_register_types(void) 86 { 87 type_register_static(&riscv_harts_info); 88 } 89 90 type_init(riscv_harts_register_types) 91