1 /* 2 * QEMU RISCV Hart Array 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Holds the state of a homogeneous array of RISC-V harts 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/module.h" 24 #include "system/reset.h" 25 #include "hw/sysbus.h" 26 #include "target/riscv/cpu.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/riscv/riscv_hart.h" 29 #include "qemu/error-report.h" 30 31 static const Property riscv_harts_props[] = { 32 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), 33 DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), 34 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), 35 DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, 36 DEFAULT_RSTVEC), 37 38 /* 39 * Smrnmi implementation-defined interrupt and exception trap handlers. 40 * 41 * When an RNMI interrupt is detected, the hart then enters M-mode and 42 * jumps to the address defined by "rnmi-interrupt-vector". 43 * 44 * When the hart encounters an exception while executing in M-mode with 45 * the mnstatus.NMIE bit clear, the hart then jumps to the address 46 * defined by "rnmi-exception-vector". 47 */ 48 DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, 49 num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, 50 uint64_t), 51 DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, 52 num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, 53 uint64_t), 54 }; 55 56 static void riscv_harts_cpu_reset(void *opaque) 57 { 58 RISCVCPU *cpu = opaque; 59 cpu_reset(CPU(cpu)); 60 } 61 62 static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, 63 char *cpu_type, Error **errp) 64 { 65 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); 66 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); 67 68 if (s->harts[idx].cfg.ext_smrnmi) { 69 if (idx < s->num_rnmi_irqvec) { 70 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), 71 "rnmi-interrupt-vector", s->rnmi_irqvec[idx]); 72 } 73 74 if (idx < s->num_rnmi_excpvec) { 75 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), 76 "rnmi-exception-vector", s->rnmi_excpvec[idx]); 77 } 78 } else { 79 if (s->num_rnmi_irqvec > 0) { 80 warn_report_once("rnmi-interrupt-vector property is ignored " 81 "because Smrnmi extension is not enabled."); 82 } 83 84 if (s->num_rnmi_excpvec > 0) { 85 warn_report_once("rnmi-exception-vector property is ignored " 86 "because Smrnmi extension is not enabled."); 87 } 88 } 89 90 s->harts[idx].env.mhartid = s->hartid_base + idx; 91 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); 92 return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); 93 } 94 95 static void riscv_harts_realize(DeviceState *dev, Error **errp) 96 { 97 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); 98 int n; 99 100 s->harts = g_new0(RISCVCPU, s->num_harts); 101 102 for (n = 0; n < s->num_harts; n++) { 103 if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { 104 return; 105 } 106 } 107 } 108 109 static void riscv_harts_class_init(ObjectClass *klass, void *data) 110 { 111 DeviceClass *dc = DEVICE_CLASS(klass); 112 113 device_class_set_props(dc, riscv_harts_props); 114 dc->realize = riscv_harts_realize; 115 } 116 117 static const TypeInfo riscv_harts_info = { 118 .name = TYPE_RISCV_HART_ARRAY, 119 .parent = TYPE_SYS_BUS_DEVICE, 120 .instance_size = sizeof(RISCVHartArrayState), 121 .class_init = riscv_harts_class_init, 122 }; 123 124 static void riscv_harts_register_types(void) 125 { 126 type_register_static(&riscv_harts_info); 127 } 128 129 type_init(riscv_harts_register_types) 130