1 /* 2 * QEMU emulation of an RISC-V IOMMU Platform Device 3 * 4 * Copyright (C) 2022-2023 Rivos Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/irq.h" 21 #include "hw/pci/pci_bus.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "qemu/host-utils.h" 27 #include "qemu/module.h" 28 #include "qom/object.h" 29 30 #include "riscv-iommu.h" 31 32 #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333 33 34 /* RISC-V IOMMU System Platform Device Emulation */ 35 36 struct RISCVIOMMUStateSys { 37 SysBusDevice parent; 38 uint64_t addr; 39 uint32_t base_irq; 40 DeviceState *irqchip; 41 RISCVIOMMUState iommu; 42 qemu_irq irqs[RISCV_IOMMU_INTR_COUNT]; 43 }; 44 45 static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, 46 unsigned vector) 47 { 48 RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu); 49 uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL); 50 51 /* We do not support MSIs yet */ 52 if (!(fctl & RISCV_IOMMU_FCTL_WSI)) { 53 return; 54 } 55 56 qemu_irq_pulse(s->irqs[vector]); 57 } 58 59 static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) 60 { 61 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev); 62 SysBusDevice *sysdev = SYS_BUS_DEVICE(s); 63 PCIBus *pci_bus; 64 qemu_irq irq; 65 66 qdev_realize(DEVICE(&s->iommu), NULL, errp); 67 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); 68 if (s->addr) { 69 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); 70 } 71 72 pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL); 73 if (pci_bus) { 74 riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); 75 } 76 77 s->iommu.notify = riscv_iommu_sysdev_notify; 78 79 /* 4 IRQs are defined starting from s->base_irq */ 80 for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) { 81 sysbus_init_irq(sysdev, &s->irqs[i]); 82 irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i); 83 sysbus_connect_irq(sysdev, i, irq); 84 } 85 } 86 87 static void riscv_iommu_sys_init(Object *obj) 88 { 89 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj); 90 RISCVIOMMUState *iommu = &s->iommu; 91 92 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); 93 qdev_alias_all_properties(DEVICE(iommu), obj); 94 95 iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS; 96 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI); 97 } 98 99 static Property riscv_iommu_sys_properties[] = { 100 DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), 101 DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0), 102 DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip, 103 TYPE_DEVICE, DeviceState *), 104 DEFINE_PROP_END_OF_LIST(), 105 }; 106 107 static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data) 108 { 109 DeviceClass *dc = DEVICE_CLASS(klass); 110 dc->realize = riscv_iommu_sys_realize; 111 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 112 device_class_set_props(dc, riscv_iommu_sys_properties); 113 } 114 115 static const TypeInfo riscv_iommu_sys = { 116 .name = TYPE_RISCV_IOMMU_SYS, 117 .parent = TYPE_SYS_BUS_DEVICE, 118 .class_init = riscv_iommu_sys_class_init, 119 .instance_init = riscv_iommu_sys_init, 120 .instance_size = sizeof(RISCVIOMMUStateSys), 121 }; 122 123 static void riscv_iommu_register_sys(void) 124 { 125 type_register_static(&riscv_iommu_sys); 126 } 127 128 type_init(riscv_iommu_register_sys) 129