1 /*
2 * QEMU emulation of an RISC-V IOMMU
3 *
4 * Copyright (C) 2022-2023 Rivos Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "hw/pci/msi.h"
21 #include "hw/pci/msix.h"
22 #include "hw/pci/pci_bus.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/riscv/riscv_hart.h"
25 #include "migration/vmstate.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28 #include "qemu/host-utils.h"
29 #include "qom/object.h"
30
31 #include "cpu_bits.h"
32 #include "riscv-iommu.h"
33 #include "riscv-iommu-bits.h"
34
35 /* RISC-V IOMMU PCI Device Emulation */
36 #define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806
37
38 /*
39 * 4 MSIx vectors for ICVEC, one for MRIF. The spec mentions in
40 * the "Placement and data flow" section that:
41 *
42 * "The interfaces related to recording an incoming MSI in a memory-resident
43 * interrupt file (MRIF) are implementation-specific. The partitioning of
44 * responsibility between the IOMMU and the IO bridge for recording the
45 * incoming MSI in an MRIF and generating the associated notice MSI are
46 * implementation-specific."
47 *
48 * We're making a design decision to create the MSIx for MRIF in the
49 * IOMMU MSIx emulation.
50 */
51 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5
52
53 /*
54 * 4 vectors that can be used by civ, fiv, pmiv and piv. Number of
55 * vectors is represented by 2^N, where N = number of writable bits
56 * in each cause. For 4 vectors we'll write 0b11 (3) in each reg.
57 */
58 #define RISCV_IOMMU_PCI_ICVEC_VECTORS 0x3333
59
60 typedef struct RISCVIOMMUStatePci {
61 PCIDevice pci; /* Parent PCIe device state */
62 uint16_t vendor_id;
63 uint16_t device_id;
64 uint8_t revision;
65 MemoryRegion bar0; /* PCI BAR (including MSI-x config) */
66 RISCVIOMMUState iommu; /* common IOMMU state */
67 } RISCVIOMMUStatePci;
68
69 /* interrupt delivery callback */
riscv_iommu_pci_notify(RISCVIOMMUState * iommu,unsigned vector)70 static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
71 {
72 RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu);
73
74 if (msix_enabled(&(s->pci))) {
75 msix_notify(&(s->pci), vector);
76 }
77 }
78
riscv_iommu_pci_realize(PCIDevice * dev,Error ** errp)79 static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp)
80 {
81 RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev);
82 RISCVIOMMUState *iommu = &s->iommu;
83 uint8_t *pci_conf = dev->config;
84 Error *err = NULL;
85
86 pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id);
87 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id);
88 pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id);
89 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id);
90 pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision);
91
92 /* Set device id for trace / debug */
93 DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x",
94 pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
95 qdev_realize(DEVICE(iommu), NULL, errp);
96
97 memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0",
98 QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE));
99 memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr);
100
101 pcie_endpoint_cap_init(dev, 0);
102
103 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
104 PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0);
105
106 int ret = msix_init(dev, RISCV_IOMMU_PCI_MSIX_VECTORS,
107 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG,
108 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err);
109
110 if (ret == -ENOTSUP) {
111 /*
112 * MSI-x is not supported by the platform.
113 * Driver should use timer/polling based notification handlers.
114 */
115 warn_report_err(err);
116 } else if (ret < 0) {
117 error_propagate(errp, err);
118 return;
119 } else {
120 /* Mark all ICVEC MSIx vectors as used */
121 for (int i = 0; i < RISCV_IOMMU_PCI_MSIX_VECTORS; i++) {
122 msix_vector_use(dev, i);
123 }
124
125 iommu->notify = riscv_iommu_pci_notify;
126 }
127
128 PCIBus *bus = pci_device_root_bus(dev);
129 if (!bus) {
130 error_setg(errp, "can't find PCIe root port for %02x:%02x.%x",
131 pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn),
132 PCI_FUNC(dev->devfn));
133 return;
134 }
135
136 riscv_iommu_pci_setup_iommu(iommu, bus, errp);
137 }
138
riscv_iommu_pci_exit(PCIDevice * pci_dev)139 static void riscv_iommu_pci_exit(PCIDevice *pci_dev)
140 {
141 pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL);
142 }
143
144 static const VMStateDescription riscv_iommu_vmstate = {
145 .name = "riscv-iommu",
146 .unmigratable = 1
147 };
148
riscv_iommu_pci_init(Object * obj)149 static void riscv_iommu_pci_init(Object *obj)
150 {
151 RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj);
152 RISCVIOMMUState *iommu = &s->iommu;
153
154 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
155 qdev_alias_all_properties(DEVICE(iommu), obj);
156
157 iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;
158 }
159
160 static Property riscv_iommu_pci_properties[] = {
161 DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id,
162 PCI_VENDOR_ID_REDHAT),
163 DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id,
164 PCI_DEVICE_ID_REDHAT_RISCV_IOMMU),
165 DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01),
166 DEFINE_PROP_END_OF_LIST(),
167 };
168
riscv_iommu_pci_class_init(ObjectClass * klass,void * data)169 static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data)
170 {
171 DeviceClass *dc = DEVICE_CLASS(klass);
172 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
173
174 k->realize = riscv_iommu_pci_realize;
175 k->exit = riscv_iommu_pci_exit;
176 k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU;
177 dc->desc = "RISCV-IOMMU DMA Remapping device";
178 dc->vmsd = &riscv_iommu_vmstate;
179 dc->hotpluggable = false;
180 dc->user_creatable = true;
181 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
182 device_class_set_props(dc, riscv_iommu_pci_properties);
183 }
184
185 static const TypeInfo riscv_iommu_pci = {
186 .name = TYPE_RISCV_IOMMU_PCI,
187 .parent = TYPE_PCI_DEVICE,
188 .class_init = riscv_iommu_pci_class_init,
189 .instance_init = riscv_iommu_pci_init,
190 .instance_size = sizeof(RISCVIOMMUStatePci),
191 .interfaces = (InterfaceInfo[]) {
192 { INTERFACE_PCIE_DEVICE },
193 { },
194 },
195 };
196
riscv_iommu_register_pci_types(void)197 static void riscv_iommu_register_pci_types(void)
198 {
199 type_register_static(&riscv_iommu_pci);
200 }
201
202 type_init(riscv_iommu_register_pci_types);
203