1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2022-2023 Rivos Inc. 4 * Copyright © 2023 FORTH-ICS/CARV 5 * Copyright © 2023 RISC-V IOMMU Task Group 6 * 7 * RISC-V IOMMU - Register Layout and Data Structures. 8 * 9 * Based on the IOMMU spec version 1.0, 3/2023 10 * https://github.com/riscv-non-isa/riscv-iommu 11 */ 12 13 #ifndef HW_RISCV_IOMMU_BITS_H 14 #define HW_RISCV_IOMMU_BITS_H 15 16 #define RISCV_IOMMU_SPEC_DOT_VER 0x010 17 18 #ifndef GENMASK_ULL 19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) 20 #endif 21 22 /* 23 * struct riscv_iommu_fq_record - Fault/Event Queue Record 24 * See section 3.2 for more info. 25 */ 26 struct riscv_iommu_fq_record { 27 uint64_t hdr; 28 uint64_t _reserved; 29 uint64_t iotval; 30 uint64_t iotval2; 31 }; 32 /* Header fields */ 33 #define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0) 34 #define RISCV_IOMMU_FQ_HDR_PID GENMASK_ULL(31, 12) 35 #define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32) 36 #define RISCV_IOMMU_FQ_HDR_TTYPE GENMASK_ULL(39, 34) 37 #define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40) 38 39 /* 40 * struct riscv_iommu_pq_record - PCIe Page Request record 41 * For more infos on the PCIe Page Request queue see chapter 3.3. 42 */ 43 struct riscv_iommu_pq_record { 44 uint64_t hdr; 45 uint64_t payload; 46 }; 47 /* Header fields */ 48 #define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12) 49 #define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32) 50 #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) 51 #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) 52 #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) 53 /* Payload fields */ 54 #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) 55 56 /* Common field positions */ 57 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) 58 #define RISCV_IOMMU_QUEUE_LOGSZ_FIELD GENMASK_ULL(4, 0) 59 #define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0) 60 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0) 61 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) 62 #define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8) 63 #define RISCV_IOMMU_QUEUE_OVERFLOW BIT(9) 64 #define RISCV_IOMMU_QUEUE_ACTIVE BIT(16) 65 #define RISCV_IOMMU_QUEUE_BUSY BIT(17) 66 #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0) 67 #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60) 68 69 /* 5.3 IOMMU Capabilities (64bits) */ 70 #define RISCV_IOMMU_REG_CAP 0x0000 71 #define RISCV_IOMMU_CAP_VERSION GENMASK_ULL(7, 0) 72 #define RISCV_IOMMU_CAP_SV32 BIT_ULL(8) 73 #define RISCV_IOMMU_CAP_SV39 BIT_ULL(9) 74 #define RISCV_IOMMU_CAP_SV48 BIT_ULL(10) 75 #define RISCV_IOMMU_CAP_SV57 BIT_ULL(11) 76 #define RISCV_IOMMU_CAP_SV32X4 BIT_ULL(16) 77 #define RISCV_IOMMU_CAP_SV39X4 BIT_ULL(17) 78 #define RISCV_IOMMU_CAP_SV48X4 BIT_ULL(18) 79 #define RISCV_IOMMU_CAP_SV57X4 BIT_ULL(19) 80 #define RISCV_IOMMU_CAP_MSI_FLAT BIT_ULL(22) 81 #define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23) 82 #define RISCV_IOMMU_CAP_ATS BIT_ULL(25) 83 #define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26) 84 #define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28) 85 #define RISCV_IOMMU_CAP_DBG BIT_ULL(31) 86 #define RISCV_IOMMU_CAP_PAS GENMASK_ULL(37, 32) 87 #define RISCV_IOMMU_CAP_PD8 BIT_ULL(38) 88 #define RISCV_IOMMU_CAP_PD17 BIT_ULL(39) 89 #define RISCV_IOMMU_CAP_PD20 BIT_ULL(40) 90 91 /* 5.4 Features control register (32bits) */ 92 #define RISCV_IOMMU_REG_FCTL 0x0008 93 #define RISCV_IOMMU_FCTL_BE BIT(0) 94 #define RISCV_IOMMU_FCTL_WSI BIT(1) 95 #define RISCV_IOMMU_FCTL_GXL BIT(2) 96 97 /* 5.5 Device-directory-table pointer (64bits) */ 98 #define RISCV_IOMMU_REG_DDTP 0x0010 99 #define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0) 100 #define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4) 101 #define RISCV_IOMMU_DDTP_PPN RISCV_IOMMU_PPN_FIELD 102 103 enum riscv_iommu_ddtp_modes { 104 RISCV_IOMMU_DDTP_MODE_OFF = 0, 105 RISCV_IOMMU_DDTP_MODE_BARE = 1, 106 RISCV_IOMMU_DDTP_MODE_1LVL = 2, 107 RISCV_IOMMU_DDTP_MODE_2LVL = 3, 108 RISCV_IOMMU_DDTP_MODE_3LVL = 4, 109 RISCV_IOMMU_DDTP_MODE_MAX = 4 110 }; 111 112 /* 5.6 Command Queue Base (64bits) */ 113 #define RISCV_IOMMU_REG_CQB 0x0018 114 #define RISCV_IOMMU_CQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD 115 #define RISCV_IOMMU_CQB_PPN RISCV_IOMMU_PPN_FIELD 116 117 /* 5.7 Command Queue head (32bits) */ 118 #define RISCV_IOMMU_REG_CQH 0x0020 119 120 /* 5.8 Command Queue tail (32bits) */ 121 #define RISCV_IOMMU_REG_CQT 0x0024 122 123 /* 5.9 Fault Queue Base (64bits) */ 124 #define RISCV_IOMMU_REG_FQB 0x0028 125 #define RISCV_IOMMU_FQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD 126 #define RISCV_IOMMU_FQB_PPN RISCV_IOMMU_PPN_FIELD 127 128 /* 5.10 Fault Queue Head (32bits) */ 129 #define RISCV_IOMMU_REG_FQH 0x0030 130 131 /* 5.11 Fault Queue tail (32bits) */ 132 #define RISCV_IOMMU_REG_FQT 0x0034 133 134 /* 5.12 Page Request Queue base (64bits) */ 135 #define RISCV_IOMMU_REG_PQB 0x0038 136 #define RISCV_IOMMU_PQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD 137 #define RISCV_IOMMU_PQB_PPN RISCV_IOMMU_PPN_FIELD 138 139 /* 5.13 Page Request Queue head (32bits) */ 140 #define RISCV_IOMMU_REG_PQH 0x0040 141 142 /* 5.14 Page Request Queue tail (32bits) */ 143 #define RISCV_IOMMU_REG_PQT 0x0044 144 145 /* 5.15 Command Queue CSR (32bits) */ 146 #define RISCV_IOMMU_REG_CQCSR 0x0048 147 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE 148 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE 149 #define RISCV_IOMMU_CQCSR_CQMF RISCV_IOMMU_QUEUE_MEM_FAULT 150 #define RISCV_IOMMU_CQCSR_CMD_TO BIT(9) 151 #define RISCV_IOMMU_CQCSR_CMD_ILL BIT(10) 152 #define RISCV_IOMMU_CQCSR_FENCE_W_IP BIT(11) 153 #define RISCV_IOMMU_CQCSR_CQON RISCV_IOMMU_QUEUE_ACTIVE 154 #define RISCV_IOMMU_CQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 155 156 /* 5.16 Fault Queue CSR (32bits) */ 157 #define RISCV_IOMMU_REG_FQCSR 0x004C 158 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE 159 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE 160 #define RISCV_IOMMU_FQCSR_FQMF RISCV_IOMMU_QUEUE_MEM_FAULT 161 #define RISCV_IOMMU_FQCSR_FQOF RISCV_IOMMU_QUEUE_OVERFLOW 162 #define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE 163 #define RISCV_IOMMU_FQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 164 165 /* 5.17 Page Request Queue CSR (32bits) */ 166 #define RISCV_IOMMU_REG_PQCSR 0x0050 167 #define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE 168 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE 169 #define RISCV_IOMMU_PQCSR_PQMF RISCV_IOMMU_QUEUE_MEM_FAULT 170 #define RISCV_IOMMU_PQCSR_PQOF RISCV_IOMMU_QUEUE_OVERFLOW 171 #define RISCV_IOMMU_PQCSR_PQON RISCV_IOMMU_QUEUE_ACTIVE 172 #define RISCV_IOMMU_PQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 173 174 /* 5.18 Interrupt Pending Status (32bits) */ 175 #define RISCV_IOMMU_REG_IPSR 0x0054 176 #define RISCV_IOMMU_IPSR_CIP BIT(0) 177 #define RISCV_IOMMU_IPSR_FIP BIT(1) 178 #define RISCV_IOMMU_IPSR_PIP BIT(3) 179 180 enum { 181 RISCV_IOMMU_INTR_CQ, 182 RISCV_IOMMU_INTR_FQ, 183 RISCV_IOMMU_INTR_PM, 184 RISCV_IOMMU_INTR_PQ, 185 RISCV_IOMMU_INTR_COUNT 186 }; 187 188 /* 5.24 Translation request IOVA (64bits) */ 189 #define RISCV_IOMMU_REG_TR_REQ_IOVA 0x0258 190 191 /* 5.25 Translation request control (64bits) */ 192 #define RISCV_IOMMU_REG_TR_REQ_CTL 0x0260 193 #define RISCV_IOMMU_TR_REQ_CTL_GO_BUSY BIT_ULL(0) 194 #define RISCV_IOMMU_TR_REQ_CTL_NW BIT_ULL(3) 195 #define RISCV_IOMMU_TR_REQ_CTL_PID GENMASK_ULL(31, 12) 196 #define RISCV_IOMMU_TR_REQ_CTL_DID GENMASK_ULL(63, 40) 197 198 /* 5.26 Translation request response (64bits) */ 199 #define RISCV_IOMMU_REG_TR_RESPONSE 0x0268 200 #define RISCV_IOMMU_TR_RESPONSE_FAULT BIT_ULL(0) 201 #define RISCV_IOMMU_TR_RESPONSE_S BIT_ULL(9) 202 #define RISCV_IOMMU_TR_RESPONSE_PPN RISCV_IOMMU_PPN_FIELD 203 204 /* 5.27 Interrupt cause to vector (64bits) */ 205 #define RISCV_IOMMU_REG_ICVEC 0x02F8 206 #define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0) 207 #define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4) 208 #define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8) 209 #define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12) 210 211 /* 5.28 MSI Configuration table (32 * 64bits) */ 212 #define RISCV_IOMMU_REG_MSI_CONFIG 0x0300 213 214 #define RISCV_IOMMU_REG_SIZE 0x1000 215 216 #define RISCV_IOMMU_DDTE_VALID BIT_ULL(0) 217 #define RISCV_IOMMU_DDTE_PPN RISCV_IOMMU_PPN_FIELD 218 219 /* Struct riscv_iommu_dc - Device Context - section 2.1 */ 220 struct riscv_iommu_dc { 221 uint64_t tc; 222 uint64_t iohgatp; 223 uint64_t ta; 224 uint64_t fsc; 225 uint64_t msiptp; 226 uint64_t msi_addr_mask; 227 uint64_t msi_addr_pattern; 228 uint64_t _reserved; 229 }; 230 231 /* Translation control fields */ 232 #define RISCV_IOMMU_DC_TC_V BIT_ULL(0) 233 #define RISCV_IOMMU_DC_TC_EN_ATS BIT_ULL(1) 234 #define RISCV_IOMMU_DC_TC_EN_PRI BIT_ULL(2) 235 #define RISCV_IOMMU_DC_TC_T2GPA BIT_ULL(3) 236 #define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4) 237 #define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5) 238 #define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6) 239 #define RISCV_IOMMU_DC_TC_GADE BIT_ULL(7) 240 #define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8) 241 #define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9) 242 #define RISCV_IOMMU_DC_TC_SBE BIT_ULL(10) 243 #define RISCV_IOMMU_DC_TC_SXL BIT_ULL(11) 244 245 /* Second-stage (aka G-stage) context fields */ 246 #define RISCV_IOMMU_DC_IOHGATP_PPN RISCV_IOMMU_ATP_PPN_FIELD 247 #define RISCV_IOMMU_DC_IOHGATP_GSCID GENMASK_ULL(59, 44) 248 #define RISCV_IOMMU_DC_IOHGATP_MODE RISCV_IOMMU_ATP_MODE_FIELD 249 250 enum riscv_iommu_dc_iohgatp_modes { 251 RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0, 252 RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8, 253 RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 = 8, 254 RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 = 9, 255 RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4 = 10 256 }; 257 258 /* Translation attributes fields */ 259 #define RISCV_IOMMU_DC_TA_PSCID GENMASK_ULL(31, 12) 260 261 /* First-stage context fields */ 262 #define RISCV_IOMMU_DC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD 263 #define RISCV_IOMMU_DC_FSC_MODE RISCV_IOMMU_ATP_MODE_FIELD 264 265 /* Generic I/O MMU command structure - check section 3.1 */ 266 struct riscv_iommu_command { 267 uint64_t dword0; 268 uint64_t dword1; 269 }; 270 271 #define RISCV_IOMMU_CMD_OPCODE GENMASK_ULL(6, 0) 272 #define RISCV_IOMMU_CMD_FUNC GENMASK_ULL(9, 7) 273 274 #define RISCV_IOMMU_CMD_IOTINVAL_OPCODE 1 275 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA 0 276 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA 1 277 #define RISCV_IOMMU_CMD_IOTINVAL_AV BIT_ULL(10) 278 #define RISCV_IOMMU_CMD_IOTINVAL_PSCID GENMASK_ULL(31, 12) 279 #define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32) 280 #define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33) 281 #define RISCV_IOMMU_CMD_IOTINVAL_GSCID GENMASK_ULL(59, 44) 282 283 #define RISCV_IOMMU_CMD_IOFENCE_OPCODE 2 284 #define RISCV_IOMMU_CMD_IOFENCE_FUNC_C 0 285 #define RISCV_IOMMU_CMD_IOFENCE_AV BIT_ULL(10) 286 #define RISCV_IOMMU_CMD_IOFENCE_DATA GENMASK_ULL(63, 32) 287 288 #define RISCV_IOMMU_CMD_IODIR_OPCODE 3 289 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT 0 290 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_PDT 1 291 #define RISCV_IOMMU_CMD_IODIR_PID GENMASK_ULL(31, 12) 292 #define RISCV_IOMMU_CMD_IODIR_DV BIT_ULL(33) 293 #define RISCV_IOMMU_CMD_IODIR_DID GENMASK_ULL(63, 40) 294 295 /* 3.1.4 I/O MMU PCIe ATS */ 296 #define RISCV_IOMMU_CMD_ATS_OPCODE 4 297 #define RISCV_IOMMU_CMD_ATS_FUNC_INVAL 0 298 #define RISCV_IOMMU_CMD_ATS_FUNC_PRGR 1 299 #define RISCV_IOMMU_CMD_ATS_PID GENMASK_ULL(31, 12) 300 #define RISCV_IOMMU_CMD_ATS_PV BIT_ULL(32) 301 #define RISCV_IOMMU_CMD_ATS_DSV BIT_ULL(33) 302 #define RISCV_IOMMU_CMD_ATS_RID GENMASK_ULL(55, 40) 303 #define RISCV_IOMMU_CMD_ATS_DSEG GENMASK_ULL(63, 56) 304 /* dword1 is the ATS payload, two different payload types for INVAL and PRGR */ 305 306 /* ATS.PRGR payload */ 307 #define RISCV_IOMMU_CMD_ATS_PRGR_RESP_CODE GENMASK_ULL(47, 44) 308 309 enum riscv_iommu_dc_fsc_atp_modes { 310 RISCV_IOMMU_DC_FSC_MODE_BARE = 0, 311 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 = 8, 312 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 = 8, 313 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 = 9, 314 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 = 10, 315 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 = 1, 316 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 = 2, 317 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 = 3 318 }; 319 320 enum riscv_iommu_fq_causes { 321 RISCV_IOMMU_FQ_CAUSE_INST_FAULT = 1, 322 RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED = 4, 323 RISCV_IOMMU_FQ_CAUSE_RD_FAULT = 5, 324 RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED = 6, 325 RISCV_IOMMU_FQ_CAUSE_WR_FAULT = 7, 326 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S = 12, 327 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S = 13, 328 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S = 15, 329 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS = 20, 330 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS = 21, 331 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS = 23, 332 RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED = 256, 333 RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT = 257, 334 RISCV_IOMMU_FQ_CAUSE_DDT_INVALID = 258, 335 RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED = 259, 336 RISCV_IOMMU_FQ_CAUSE_TTYPE_BLOCKED = 260, 337 RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT = 261, 338 RISCV_IOMMU_FQ_CAUSE_MSI_INVALID = 262, 339 RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED = 263, 340 RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT = 264, 341 RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT = 265, 342 RISCV_IOMMU_FQ_CAUSE_PDT_INVALID = 266, 343 RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED = 267, 344 RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED = 268, 345 RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED = 269, 346 RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED = 270, 347 RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED = 271, 348 RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR = 272, 349 RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT = 273, 350 RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED = 274 351 }; 352 353 /* MSI page table pointer */ 354 #define RISCV_IOMMU_DC_MSIPTP_PPN RISCV_IOMMU_ATP_PPN_FIELD 355 #define RISCV_IOMMU_DC_MSIPTP_MODE RISCV_IOMMU_ATP_MODE_FIELD 356 #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 357 #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 358 359 /* Translation attributes fields */ 360 #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) 361 #define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32) 362 363 /* First stage context fields */ 364 #define RISCV_IOMMU_PC_FSC_PPN GENMASK_ULL(43, 0) 365 #define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44) 366 367 enum riscv_iommu_fq_ttypes { 368 RISCV_IOMMU_FQ_TTYPE_NONE = 0, 369 RISCV_IOMMU_FQ_TTYPE_UADDR_INST_FETCH = 1, 370 RISCV_IOMMU_FQ_TTYPE_UADDR_RD = 2, 371 RISCV_IOMMU_FQ_TTYPE_UADDR_WR = 3, 372 RISCV_IOMMU_FQ_TTYPE_TADDR_INST_FETCH = 5, 373 RISCV_IOMMU_FQ_TTYPE_TADDR_RD = 6, 374 RISCV_IOMMU_FQ_TTYPE_TADDR_WR = 7, 375 RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ = 8, 376 RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9, 377 }; 378 379 /* Header fields */ 380 #define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12) 381 #define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32) 382 #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) 383 #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) 384 #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) 385 386 /* Payload fields */ 387 #define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) 388 #define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) 389 #define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) 390 #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) 391 #define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) 392 #define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) 393 394 395 /* 396 * struct riscv_iommu_msi_pte - MSI Page Table Entry 397 */ 398 struct riscv_iommu_msi_pte { 399 uint64_t pte; 400 uint64_t mrif_info; 401 }; 402 403 /* Fields on pte */ 404 #define RISCV_IOMMU_MSI_PTE_V BIT_ULL(0) 405 #define RISCV_IOMMU_MSI_PTE_M GENMASK_ULL(2, 1) 406 407 #define RISCV_IOMMU_MSI_PTE_M_MRIF 1 408 #define RISCV_IOMMU_MSI_PTE_M_BASIC 3 409 410 /* When M == 1 (MRIF mode) */ 411 #define RISCV_IOMMU_MSI_PTE_MRIF_ADDR GENMASK_ULL(53, 7) 412 /* When M == 3 (basic mode) */ 413 #define RISCV_IOMMU_MSI_PTE_PPN RISCV_IOMMU_PPN_FIELD 414 #define RISCV_IOMMU_MSI_PTE_C BIT_ULL(63) 415 416 /* Fields on mrif_info */ 417 #define RISCV_IOMMU_MSI_MRIF_NID GENMASK_ULL(9, 0) 418 #define RISCV_IOMMU_MSI_MRIF_NPPN RISCV_IOMMU_PPN_FIELD 419 #define RISCV_IOMMU_MSI_MRIF_NID_MSB BIT_ULL(60) 420 421 #endif /* _RISCV_IOMMU_BITS_H_ */ 422