1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * Provides a board compatible with the OpenTitan FPGA platform: 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "hw/riscv/opentitan.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/misc/unimp.h" 27 #include "hw/riscv/boot.h" 28 #include "qemu/units.h" 29 #include "sysemu/sysemu.h" 30 31 static const MemMapEntry ibex_memmap[] = { 32 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB }, 33 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 }, 34 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 }, 35 [IBEX_DEV_UART] = { 0x40000000, 0x1000 }, 36 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 }, 37 [IBEX_DEV_SPI] = { 0x40050000, 0x1000 }, 38 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, 39 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, 40 [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 }, 41 [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, 42 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, 43 [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 }, 44 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, 45 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 }, 46 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 }, 47 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, 48 [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 }, 49 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 }, 50 [IBEX_DEV_AES] = { 0x41100000, 0x1000 }, 51 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, 52 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, 53 [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, 54 [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 }, 55 [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 }, 56 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 }, 57 [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 }, 58 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 }, 59 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 }, 60 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, 61 [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, 62 [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 }, 63 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, 64 }; 65 66 static void opentitan_board_init(MachineState *machine) 67 { 68 MachineClass *mc = MACHINE_GET_CLASS(machine); 69 const MemMapEntry *memmap = ibex_memmap; 70 OpenTitanState *s = g_new0(OpenTitanState, 1); 71 MemoryRegion *sys_mem = get_system_memory(); 72 73 if (machine->ram_size != mc->default_ram_size) { 74 char *sz = size_to_str(mc->default_ram_size); 75 error_report("Invalid RAM size, should be %s", sz); 76 g_free(sz); 77 exit(EXIT_FAILURE); 78 } 79 80 /* Initialize SoC */ 81 object_initialize_child(OBJECT(machine), "soc", &s->soc, 82 TYPE_RISCV_IBEX_SOC); 83 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 84 85 memory_region_add_subregion(sys_mem, 86 memmap[IBEX_DEV_RAM].base, machine->ram); 87 88 if (machine->firmware) { 89 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL); 90 } 91 92 if (machine->kernel_filename) { 93 riscv_load_kernel(machine->kernel_filename, 94 memmap[IBEX_DEV_RAM].base, NULL); 95 } 96 } 97 98 static void opentitan_machine_init(MachineClass *mc) 99 { 100 mc->desc = "RISC-V Board compatible with OpenTitan"; 101 mc->init = opentitan_board_init; 102 mc->max_cpus = 1; 103 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 104 mc->default_ram_id = "riscv.lowrisc.ibex.ram"; 105 mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; 106 } 107 108 DEFINE_MACHINE("opentitan", opentitan_machine_init) 109 110 static void lowrisc_ibex_soc_init(Object *obj) 111 { 112 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 113 114 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 115 116 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); 117 118 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); 119 120 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); 121 } 122 123 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 124 { 125 const MemMapEntry *memmap = ibex_memmap; 126 MachineState *ms = MACHINE(qdev_get_machine()); 127 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 128 MemoryRegion *sys_mem = get_system_memory(); 129 int i; 130 131 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 132 &error_abort); 133 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 134 &error_abort); 135 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort); 136 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 137 138 /* Boot ROM */ 139 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 140 memmap[IBEX_DEV_ROM].size, &error_fatal); 141 memory_region_add_subregion(sys_mem, 142 memmap[IBEX_DEV_ROM].base, &s->rom); 143 144 /* Flash memory */ 145 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 146 memmap[IBEX_DEV_FLASH].size, &error_fatal); 147 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 148 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, 149 memmap[IBEX_DEV_FLASH_VIRTUAL].size); 150 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, 151 &s->flash_mem); 152 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base, 153 &s->flash_alias); 154 155 /* PLIC */ 156 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); 157 qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0); 158 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); 159 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); 160 qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00); 161 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); 162 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); 163 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18); 164 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); 165 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); 166 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); 167 168 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { 169 return; 170 } 171 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); 172 173 for (i = 0; i < ms->smp.cpus; i++) { 174 CPUState *cpu = qemu_get_cpu(i); 175 176 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, 177 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); 178 } 179 180 /* UART */ 181 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); 182 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 183 return; 184 } 185 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); 186 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 187 0, qdev_get_gpio_in(DEVICE(&s->plic), 188 IBEX_UART0_TX_WATERMARK_IRQ)); 189 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 190 1, qdev_get_gpio_in(DEVICE(&s->plic), 191 IBEX_UART0_RX_WATERMARK_IRQ)); 192 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 193 2, qdev_get_gpio_in(DEVICE(&s->plic), 194 IBEX_UART0_TX_EMPTY_IRQ)); 195 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 196 3, qdev_get_gpio_in(DEVICE(&s->plic), 197 IBEX_UART0_RX_OVERFLOW_IRQ)); 198 199 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 200 return; 201 } 202 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); 203 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 204 0, qdev_get_gpio_in(DEVICE(&s->plic), 205 IBEX_TIMER_TIMEREXPIRED0_0)); 206 qdev_connect_gpio_out(DEVICE(&s->timer), 0, 207 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), 208 IRQ_M_TIMER)); 209 210 create_unimplemented_device("riscv.lowrisc.ibex.gpio", 211 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 212 create_unimplemented_device("riscv.lowrisc.ibex.spi", 213 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size); 214 create_unimplemented_device("riscv.lowrisc.ibex.i2c", 215 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); 216 create_unimplemented_device("riscv.lowrisc.ibex.pattgen", 217 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); 218 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", 219 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); 220 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", 221 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); 222 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 223 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); 224 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 225 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); 226 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 227 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); 228 create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 229 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); 230 create_unimplemented_device("riscv.lowrisc.ibex.padctrl", 231 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); 232 create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 233 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); 234 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 235 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); 236 create_unimplemented_device("riscv.lowrisc.ibex.aes", 237 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); 238 create_unimplemented_device("riscv.lowrisc.ibex.hmac", 239 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); 240 create_unimplemented_device("riscv.lowrisc.ibex.kmac", 241 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); 242 create_unimplemented_device("riscv.lowrisc.ibex.keymgr", 243 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); 244 create_unimplemented_device("riscv.lowrisc.ibex.csrng", 245 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); 246 create_unimplemented_device("riscv.lowrisc.ibex.entropy", 247 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); 248 create_unimplemented_device("riscv.lowrisc.ibex.edn0", 249 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); 250 create_unimplemented_device("riscv.lowrisc.ibex.edn1", 251 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); 252 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 253 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); 254 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", 255 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); 256 create_unimplemented_device("riscv.lowrisc.ibex.otbn", 257 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); 258 create_unimplemented_device("riscv.lowrisc.ibex.peri", 259 memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); 260 } 261 262 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 263 { 264 DeviceClass *dc = DEVICE_CLASS(oc); 265 266 dc->realize = lowrisc_ibex_soc_realize; 267 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 268 dc->user_creatable = false; 269 } 270 271 static const TypeInfo lowrisc_ibex_soc_type_info = { 272 .name = TYPE_RISCV_IBEX_SOC, 273 .parent = TYPE_DEVICE, 274 .instance_size = sizeof(LowRISCIbexSoCState), 275 .instance_init = lowrisc_ibex_soc_init, 276 .class_init = lowrisc_ibex_soc_class_init, 277 }; 278 279 static void lowrisc_ibex_soc_register_types(void) 280 { 281 type_register_static(&lowrisc_ibex_soc_type_info); 282 } 283 284 type_init(lowrisc_ibex_soc_register_types) 285