1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * Provides a board compatible with the OpenTitan FPGA platform: 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "hw/riscv/opentitan.h" 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "hw/boards.h" 27 #include "hw/misc/unimp.h" 28 #include "hw/riscv/boot.h" 29 #include "qemu/units.h" 30 #include "sysemu/sysemu.h" 31 32 /* 33 * This version of the OpenTitan machine currently supports 34 * OpenTitan RTL version: 35 * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47> 36 * 37 * MMIO mapping as per (specified commit): 38 * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h 39 */ 40 static const MemMapEntry ibex_memmap[] = { 41 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, 42 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, 43 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, 44 [IBEX_DEV_UART] = { 0x40000000, 0x40 }, 45 [IBEX_DEV_GPIO] = { 0x40040000, 0x40 }, 46 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 }, 47 [IBEX_DEV_I2C] = { 0x40080000, 0x80 }, 48 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 }, 49 [IBEX_DEV_TIMER] = { 0x40100000, 0x200 }, 50 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 }, 51 [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 }, 52 [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 }, 53 [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 }, 54 [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 }, 55 [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 }, 56 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 }, 57 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 }, 58 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 }, 59 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, 60 [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 }, 61 [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 }, 62 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 }, 63 [IBEX_DEV_AES] = { 0x41100000, 0x100 }, 64 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, 65 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, 66 [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, 67 [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 }, 68 [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 }, 69 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 }, 70 [IBEX_DEV_EDNO] = { 0x41170000, 0x80 }, 71 [IBEX_DEV_EDN1] = { 0x41180000, 0x80 }, 72 [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 }, 73 [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 }, 74 [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 }, 75 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, 76 }; 77 78 static void opentitan_machine_init(MachineState *machine) 79 { 80 MachineClass *mc = MACHINE_GET_CLASS(machine); 81 OpenTitanState *s = OPENTITAN_MACHINE(machine); 82 const MemMapEntry *memmap = ibex_memmap; 83 MemoryRegion *sys_mem = get_system_memory(); 84 85 if (machine->ram_size != mc->default_ram_size) { 86 char *sz = size_to_str(mc->default_ram_size); 87 error_report("Invalid RAM size, should be %s", sz); 88 g_free(sz); 89 exit(EXIT_FAILURE); 90 } 91 92 /* Initialize SoC */ 93 object_initialize_child(OBJECT(machine), "soc", &s->soc, 94 TYPE_RISCV_IBEX_SOC); 95 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 96 97 memory_region_add_subregion(sys_mem, 98 memmap[IBEX_DEV_RAM].base, machine->ram); 99 100 if (machine->firmware) { 101 hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base; 102 riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); 103 } 104 105 if (machine->kernel_filename) { 106 riscv_load_kernel(machine, &s->soc.cpus, 107 memmap[IBEX_DEV_RAM].base, 108 false, NULL); 109 } 110 } 111 112 static void opentitan_machine_class_init(ObjectClass *oc, void *data) 113 { 114 MachineClass *mc = MACHINE_CLASS(oc); 115 116 mc->desc = "RISC-V Board compatible with OpenTitan"; 117 mc->init = opentitan_machine_init; 118 mc->max_cpus = 1; 119 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 120 mc->default_ram_id = "riscv.lowrisc.ibex.ram"; 121 mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; 122 } 123 124 static void lowrisc_ibex_soc_init(Object *obj) 125 { 126 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 127 128 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 129 130 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); 131 132 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); 133 134 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); 135 136 for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { 137 object_initialize_child(obj, "spi_host[*]", &s->spi_host[i], 138 TYPE_IBEX_SPI_HOST); 139 } 140 } 141 142 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 143 { 144 const MemMapEntry *memmap = ibex_memmap; 145 DeviceState *dev; 146 SysBusDevice *busdev; 147 MachineState *ms = MACHINE(qdev_get_machine()); 148 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 149 MemoryRegion *sys_mem = get_system_memory(); 150 int i; 151 152 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 153 &error_abort); 154 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 155 &error_abort); 156 object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec, 157 &error_abort); 158 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); 159 160 /* Boot ROM */ 161 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 162 memmap[IBEX_DEV_ROM].size, &error_fatal); 163 memory_region_add_subregion(sys_mem, 164 memmap[IBEX_DEV_ROM].base, &s->rom); 165 166 /* Flash memory */ 167 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 168 memmap[IBEX_DEV_FLASH].size, &error_fatal); 169 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 170 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, 171 memmap[IBEX_DEV_FLASH_VIRTUAL].size); 172 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, 173 &s->flash_mem); 174 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base, 175 &s->flash_alias); 176 177 /* PLIC */ 178 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); 179 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); 180 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); 181 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); 182 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); 183 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); 184 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); 185 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); 186 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); 187 188 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { 189 return; 190 } 191 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); 192 193 for (i = 0; i < ms->smp.cpus; i++) { 194 CPUState *cpu = qemu_get_cpu(i); 195 196 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, 197 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); 198 } 199 200 /* UART */ 201 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); 202 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 203 return; 204 } 205 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); 206 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 207 0, qdev_get_gpio_in(DEVICE(&s->plic), 208 IBEX_UART0_TX_WATERMARK_IRQ)); 209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 210 1, qdev_get_gpio_in(DEVICE(&s->plic), 211 IBEX_UART0_RX_WATERMARK_IRQ)); 212 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 213 2, qdev_get_gpio_in(DEVICE(&s->plic), 214 IBEX_UART0_TX_EMPTY_IRQ)); 215 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 216 3, qdev_get_gpio_in(DEVICE(&s->plic), 217 IBEX_UART0_RX_OVERFLOW_IRQ)); 218 219 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 220 return; 221 } 222 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); 223 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 224 0, qdev_get_gpio_in(DEVICE(&s->plic), 225 IBEX_TIMER_TIMEREXPIRED0_0)); 226 qdev_connect_gpio_out(DEVICE(&s->timer), 0, 227 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), 228 IRQ_M_TIMER)); 229 230 /* SPI-Hosts */ 231 for (i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) { 232 dev = DEVICE(&(s->spi_host[i])); 233 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) { 234 return; 235 } 236 busdev = SYS_BUS_DEVICE(dev); 237 sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base); 238 239 switch (i) { 240 case OPENTITAN_SPI_HOST0: 241 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), 242 IBEX_SPI_HOST0_ERR_IRQ)); 243 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), 244 IBEX_SPI_HOST0_SPI_EVENT_IRQ)); 245 break; 246 case OPENTITAN_SPI_HOST1: 247 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), 248 IBEX_SPI_HOST1_ERR_IRQ)); 249 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), 250 IBEX_SPI_HOST1_SPI_EVENT_IRQ)); 251 break; 252 } 253 } 254 255 create_unimplemented_device("riscv.lowrisc.ibex.gpio", 256 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 257 create_unimplemented_device("riscv.lowrisc.ibex.spi_device", 258 memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size); 259 create_unimplemented_device("riscv.lowrisc.ibex.i2c", 260 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); 261 create_unimplemented_device("riscv.lowrisc.ibex.pattgen", 262 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); 263 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", 264 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); 265 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", 266 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); 267 create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl", 268 memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size); 269 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 270 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); 271 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 272 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); 273 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 274 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); 275 create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 276 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); 277 create_unimplemented_device("riscv.lowrisc.ibex.aon_timer", 278 memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size); 279 create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 280 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); 281 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 282 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); 283 create_unimplemented_device("riscv.lowrisc.ibex.aes", 284 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); 285 create_unimplemented_device("riscv.lowrisc.ibex.hmac", 286 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); 287 create_unimplemented_device("riscv.lowrisc.ibex.kmac", 288 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); 289 create_unimplemented_device("riscv.lowrisc.ibex.keymgr", 290 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); 291 create_unimplemented_device("riscv.lowrisc.ibex.csrng", 292 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); 293 create_unimplemented_device("riscv.lowrisc.ibex.entropy", 294 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); 295 create_unimplemented_device("riscv.lowrisc.ibex.edn0", 296 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); 297 create_unimplemented_device("riscv.lowrisc.ibex.edn1", 298 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); 299 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 300 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); 301 create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl", 302 memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size); 303 create_unimplemented_device("riscv.lowrisc.ibex.otbn", 304 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); 305 create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg", 306 memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size); 307 } 308 309 static Property lowrisc_ibex_soc_props[] = { 310 DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400), 311 DEFINE_PROP_END_OF_LIST() 312 }; 313 314 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 315 { 316 DeviceClass *dc = DEVICE_CLASS(oc); 317 318 device_class_set_props(dc, lowrisc_ibex_soc_props); 319 dc->realize = lowrisc_ibex_soc_realize; 320 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 321 dc->user_creatable = false; 322 } 323 324 static const TypeInfo open_titan_types[] = { 325 { 326 .name = TYPE_RISCV_IBEX_SOC, 327 .parent = TYPE_DEVICE, 328 .instance_size = sizeof(LowRISCIbexSoCState), 329 .instance_init = lowrisc_ibex_soc_init, 330 .class_init = lowrisc_ibex_soc_class_init, 331 }, { 332 .name = TYPE_OPENTITAN_MACHINE, 333 .parent = TYPE_MACHINE, 334 .instance_size = sizeof(OpenTitanState), 335 .class_init = opentitan_machine_class_init, 336 } 337 }; 338 339 DEFINE_TYPES(open_titan_types) 340