1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * Provides a board compatible with the OpenTitan FPGA platform: 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/riscv/opentitan.h" 23 #include "qapi/error.h" 24 #include "hw/boards.h" 25 #include "hw/misc/unimp.h" 26 #include "hw/riscv/boot.h" 27 #include "exec/address-spaces.h" 28 29 static const struct MemmapEntry { 30 hwaddr base; 31 hwaddr size; 32 } ibex_memmap[] = { 33 [IBEX_ROM] = { 0x00008000, 0xc000 }, 34 [IBEX_RAM] = { 0x10000000, 0x10000 }, 35 [IBEX_FLASH] = { 0x20000000, 0x80000 }, 36 [IBEX_UART] = { 0x40000000, 0x10000 }, 37 [IBEX_GPIO] = { 0x40010000, 0x10000 }, 38 [IBEX_SPI] = { 0x40020000, 0x10000 }, 39 [IBEX_FLASH_CTRL] = { 0x40030000, 0x10000 }, 40 [IBEX_PINMUX] = { 0x40070000, 0x10000 }, 41 [IBEX_RV_TIMER] = { 0x40080000, 0x10000 }, 42 [IBEX_PLIC] = { 0x40090000, 0x10000 }, 43 [IBEX_PWRMGR] = { 0x400A0000, 0x10000 }, 44 [IBEX_RSTMGR] = { 0x400B0000, 0x10000 }, 45 [IBEX_CLKMGR] = { 0x400C0000, 0x10000 }, 46 [IBEX_AES] = { 0x40110000, 0x10000 }, 47 [IBEX_HMAC] = { 0x40120000, 0x10000 }, 48 [IBEX_ALERT_HANDLER] = { 0x40130000, 0x10000 }, 49 [IBEX_NMI_GEN] = { 0x40140000, 0x10000 }, 50 [IBEX_USBDEV] = { 0x40150000, 0x10000 }, 51 [IBEX_PADCTRL] = { 0x40160000, 0x10000 } 52 }; 53 54 static void riscv_opentitan_init(MachineState *machine) 55 { 56 const struct MemmapEntry *memmap = ibex_memmap; 57 OpenTitanState *s = g_new0(OpenTitanState, 1); 58 MemoryRegion *sys_mem = get_system_memory(); 59 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 60 61 /* Initialize SoC */ 62 object_initialize_child(OBJECT(machine), "soc", &s->soc, 63 sizeof(s->soc), TYPE_RISCV_IBEX_SOC, 64 &error_abort, NULL); 65 object_property_set_bool(OBJECT(&s->soc), true, "realized", 66 &error_abort); 67 68 memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", 69 memmap[IBEX_RAM].size, &error_fatal); 70 memory_region_add_subregion(sys_mem, 71 memmap[IBEX_RAM].base, main_mem); 72 73 74 if (machine->firmware) { 75 riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL); 76 } 77 78 if (machine->kernel_filename) { 79 riscv_load_kernel(machine->kernel_filename, NULL); 80 } 81 } 82 83 static void riscv_opentitan_machine_init(MachineClass *mc) 84 { 85 mc->desc = "RISC-V Board compatible with OpenTitan"; 86 mc->init = riscv_opentitan_init; 87 mc->max_cpus = 1; 88 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 89 } 90 91 DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init) 92 93 static void riscv_lowrisc_ibex_soc_init(Object *obj) 94 { 95 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 96 97 object_initialize_child(obj, "cpus", &s->cpus, 98 sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, 99 &error_abort, NULL); 100 } 101 102 static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 103 { 104 const struct MemmapEntry *memmap = ibex_memmap; 105 MachineState *ms = MACHINE(qdev_get_machine()); 106 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 107 MemoryRegion *sys_mem = get_system_memory(); 108 109 object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", 110 &error_abort); 111 object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 112 &error_abort); 113 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 114 &error_abort); 115 116 /* Boot ROM */ 117 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 118 memmap[IBEX_ROM].size, &error_fatal); 119 memory_region_add_subregion(sys_mem, 120 memmap[IBEX_ROM].base, &s->rom); 121 122 /* Flash memory */ 123 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 124 memmap[IBEX_FLASH].size, &error_fatal); 125 memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base, 126 &s->flash_mem); 127 128 create_unimplemented_device("riscv.lowrisc.ibex.uart", 129 memmap[IBEX_UART].base, memmap[IBEX_UART].size); 130 create_unimplemented_device("riscv.lowrisc.ibex.gpio", 131 memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size); 132 create_unimplemented_device("riscv.lowrisc.ibex.spi", 133 memmap[IBEX_SPI].base, memmap[IBEX_SPI].size); 134 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 135 memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size); 136 create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", 137 memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size); 138 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 139 memmap[IBEX_PWRMGR].base, memmap[IBEX_PWRMGR].size); 140 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 141 memmap[IBEX_RSTMGR].base, memmap[IBEX_RSTMGR].size); 142 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 143 memmap[IBEX_CLKMGR].base, memmap[IBEX_CLKMGR].size); 144 create_unimplemented_device("riscv.lowrisc.ibex.aes", 145 memmap[IBEX_AES].base, memmap[IBEX_AES].size); 146 create_unimplemented_device("riscv.lowrisc.ibex.hmac", 147 memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size); 148 create_unimplemented_device("riscv.lowrisc.ibex.plic", 149 memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size); 150 create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 151 memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size); 152 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 153 memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size); 154 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", 155 memmap[IBEX_NMI_GEN].base, memmap[IBEX_NMI_GEN].size); 156 create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 157 memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size); 158 create_unimplemented_device("riscv.lowrisc.ibex.padctrl", 159 memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size); 160 } 161 162 static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 163 { 164 DeviceClass *dc = DEVICE_CLASS(oc); 165 166 dc->realize = riscv_lowrisc_ibex_soc_realize; 167 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 168 dc->user_creatable = false; 169 } 170 171 static const TypeInfo riscv_lowrisc_ibex_soc_type_info = { 172 .name = TYPE_RISCV_IBEX_SOC, 173 .parent = TYPE_DEVICE, 174 .instance_size = sizeof(LowRISCIbexSoCState), 175 .instance_init = riscv_lowrisc_ibex_soc_init, 176 .class_init = riscv_lowrisc_ibex_soc_class_init, 177 }; 178 179 static void riscv_lowrisc_ibex_soc_register_types(void) 180 { 181 type_register_static(&riscv_lowrisc_ibex_soc_type_info); 182 } 183 184 type_init(riscv_lowrisc_ibex_soc_register_types) 185