1 /* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * Provides a board compatible with the OpenTitan FPGA platform: 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/riscv/opentitan.h" 23 #include "qapi/error.h" 24 #include "hw/boards.h" 25 #include "hw/misc/unimp.h" 26 #include "hw/riscv/boot.h" 27 #include "exec/address-spaces.h" 28 #include "qemu/units.h" 29 #include "sysemu/sysemu.h" 30 31 static const struct MemmapEntry { 32 hwaddr base; 33 hwaddr size; 34 } ibex_memmap[] = { 35 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB }, 36 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 }, 37 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 }, 38 [IBEX_DEV_UART] = { 0x40000000, 0x10000 }, 39 [IBEX_DEV_GPIO] = { 0x40010000, 0x10000 }, 40 [IBEX_DEV_SPI] = { 0x40020000, 0x10000 }, 41 [IBEX_DEV_FLASH_CTRL] = { 0x40030000, 0x10000 }, 42 [IBEX_DEV_PINMUX] = { 0x40070000, 0x10000 }, 43 [IBEX_DEV_RV_TIMER] = { 0x40080000, 0x10000 }, 44 [IBEX_DEV_PLIC] = { 0x40090000, 0x10000 }, 45 [IBEX_DEV_PWRMGR] = { 0x400A0000, 0x10000 }, 46 [IBEX_DEV_RSTMGR] = { 0x400B0000, 0x10000 }, 47 [IBEX_DEV_CLKMGR] = { 0x400C0000, 0x10000 }, 48 [IBEX_DEV_AES] = { 0x40110000, 0x10000 }, 49 [IBEX_DEV_HMAC] = { 0x40120000, 0x10000 }, 50 [IBEX_DEV_ALERT_HANDLER] = { 0x40130000, 0x10000 }, 51 [IBEX_DEV_NMI_GEN] = { 0x40140000, 0x10000 }, 52 [IBEX_DEV_USBDEV] = { 0x40150000, 0x10000 }, 53 [IBEX_DEV_PADCTRL] = { 0x40160000, 0x10000 } 54 }; 55 56 static void opentitan_board_init(MachineState *machine) 57 { 58 const struct MemmapEntry *memmap = ibex_memmap; 59 OpenTitanState *s = g_new0(OpenTitanState, 1); 60 MemoryRegion *sys_mem = get_system_memory(); 61 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 62 63 /* Initialize SoC */ 64 object_initialize_child(OBJECT(machine), "soc", &s->soc, 65 TYPE_RISCV_IBEX_SOC); 66 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 67 68 memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", 69 memmap[IBEX_DEV_RAM].size, &error_fatal); 70 memory_region_add_subregion(sys_mem, 71 memmap[IBEX_DEV_RAM].base, main_mem); 72 73 if (machine->firmware) { 74 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL); 75 } 76 77 if (machine->kernel_filename) { 78 riscv_load_kernel(machine->kernel_filename, NULL); 79 } 80 } 81 82 static void opentitan_machine_init(MachineClass *mc) 83 { 84 mc->desc = "RISC-V Board compatible with OpenTitan"; 85 mc->init = opentitan_board_init; 86 mc->max_cpus = 1; 87 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 88 } 89 90 DEFINE_MACHINE("opentitan", opentitan_machine_init) 91 92 static void lowrisc_ibex_soc_init(Object *obj) 93 { 94 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 95 96 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 97 98 object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); 99 100 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); 101 } 102 103 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 104 { 105 const struct MemmapEntry *memmap = ibex_memmap; 106 MachineState *ms = MACHINE(qdev_get_machine()); 107 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 108 MemoryRegion *sys_mem = get_system_memory(); 109 110 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 111 &error_abort); 112 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 113 &error_abort); 114 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); 115 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 116 117 /* Boot ROM */ 118 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 119 memmap[IBEX_DEV_ROM].size, &error_fatal); 120 memory_region_add_subregion(sys_mem, 121 memmap[IBEX_DEV_ROM].base, &s->rom); 122 123 /* Flash memory */ 124 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 125 memmap[IBEX_DEV_FLASH].size, &error_fatal); 126 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, 127 &s->flash_mem); 128 129 /* PLIC */ 130 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { 131 return; 132 } 133 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); 134 135 /* UART */ 136 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); 137 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 138 return; 139 } 140 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); 141 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 142 0, qdev_get_gpio_in(DEVICE(&s->plic), 143 IBEX_UART_TX_WATERMARK_IRQ)); 144 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 145 1, qdev_get_gpio_in(DEVICE(&s->plic), 146 IBEX_UART_RX_WATERMARK_IRQ)); 147 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 148 2, qdev_get_gpio_in(DEVICE(&s->plic), 149 IBEX_UART_TX_EMPTY_IRQ)); 150 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 151 3, qdev_get_gpio_in(DEVICE(&s->plic), 152 IBEX_UART_RX_OVERFLOW_IRQ)); 153 154 create_unimplemented_device("riscv.lowrisc.ibex.gpio", 155 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 156 create_unimplemented_device("riscv.lowrisc.ibex.spi", 157 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size); 158 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 159 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); 160 create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", 161 memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size); 162 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 163 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); 164 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 165 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); 166 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 167 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); 168 create_unimplemented_device("riscv.lowrisc.ibex.aes", 169 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); 170 create_unimplemented_device("riscv.lowrisc.ibex.hmac", 171 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); 172 create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 173 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); 174 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 175 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); 176 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", 177 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); 178 create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 179 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); 180 create_unimplemented_device("riscv.lowrisc.ibex.padctrl", 181 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); 182 } 183 184 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 185 { 186 DeviceClass *dc = DEVICE_CLASS(oc); 187 188 dc->realize = lowrisc_ibex_soc_realize; 189 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 190 dc->user_creatable = false; 191 } 192 193 static const TypeInfo lowrisc_ibex_soc_type_info = { 194 .name = TYPE_RISCV_IBEX_SOC, 195 .parent = TYPE_DEVICE, 196 .instance_size = sizeof(LowRISCIbexSoCState), 197 .instance_init = lowrisc_ibex_soc_init, 198 .class_init = lowrisc_ibex_soc_class_init, 199 }; 200 201 static void lowrisc_ibex_soc_register_types(void) 202 { 203 type_register_static(&lowrisc_ibex_soc_type_info); 204 } 205 206 type_init(lowrisc_ibex_soc_register_types) 207