1 /* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 10 * 11 * 0) CLINT (Core Level Interruptor) 12 * 1) PLIC (Platform Level Interrupt Controller) 13 * 2) eNVM (Embedded Non-Volatile Memory) 14 * 3) MMUARTs (Multi-Mode UART) 15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it 16 * 5) SiFive Platform DMA (Direct Memory Access Controller) 17 * 6) GEM (Gigabit Ethernet MAC Controller) 18 * 7) DMC (DDR Memory Controller) 19 * 8) IOSCB modules 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qemu/log.h" 40 #include "qemu/units.h" 41 #include "qemu/cutils.h" 42 #include "qapi/error.h" 43 #include "hw/boards.h" 44 #include "hw/irq.h" 45 #include "hw/loader.h" 46 #include "hw/sysbus.h" 47 #include "chardev/char.h" 48 #include "hw/cpu/cluster.h" 49 #include "target/riscv/cpu.h" 50 #include "hw/misc/unimp.h" 51 #include "hw/riscv/boot.h" 52 #include "hw/riscv/riscv_hart.h" 53 #include "hw/riscv/microchip_pfsoc.h" 54 #include "hw/intc/sifive_clint.h" 55 #include "hw/intc/sifive_plic.h" 56 #include "sysemu/sysemu.h" 57 58 /* 59 * The BIOS image used by this machine is called Hart Software Services (HSS). 60 * See https://github.com/polarfire-soc/hart-software-services 61 */ 62 #define BIOS_FILENAME "hss.bin" 63 #define RESET_VECTOR 0x20220000 64 65 /* CLINT timebase frequency */ 66 #define CLINT_TIMEBASE_FREQ 1000000 67 68 /* GEM version */ 69 #define GEM_REVISION 0x0107010c 70 71 /* 72 * The complete description of the whole PolarFire SoC memory map is scattered 73 * in different documents. There are several places to look at for memory maps: 74 * 75 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 76 * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 77 * https://www.microsemi.com/document-portal/doc_download/ 78 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 79 * describes the whole picture of the PolarFire SoC memory map. 80 * 81 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 82 * https://www.microsemi.com/document-portal/doc_download/ 83 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 84 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 85 * describes the complete integrated peripherals memory map 86 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 87 * describes the complete IOSCB modules memory maps 88 */ 89 static const MemMapEntry microchip_pfsoc_memmap[] = { 90 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 91 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 92 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 93 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 94 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 95 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 96 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 97 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 98 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 99 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 100 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 101 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 102 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 103 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 104 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 105 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 106 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 107 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 108 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 109 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 110 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 111 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 112 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 113 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, 114 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, 115 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, 116 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 117 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 118 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 119 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 120 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 121 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 122 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 123 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, 124 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 125 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, 126 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, 127 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, 128 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, 129 }; 130 131 static void microchip_pfsoc_soc_instance_init(Object *obj) 132 { 133 MachineState *ms = MACHINE(qdev_get_machine()); 134 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 135 136 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 137 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 138 139 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 140 TYPE_RISCV_HART_ARRAY); 141 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 142 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 143 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 144 TYPE_RISCV_CPU_SIFIVE_E51); 145 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 146 147 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 148 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 149 150 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 151 TYPE_RISCV_HART_ARRAY); 152 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 153 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 154 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 155 TYPE_RISCV_CPU_SIFIVE_U54); 156 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 157 158 object_initialize_child(obj, "dma-controller", &s->dma, 159 TYPE_SIFIVE_PDMA); 160 161 object_initialize_child(obj, "sysreg", &s->sysreg, 162 TYPE_MCHP_PFSOC_SYSREG); 163 164 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 165 TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 166 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 167 TYPE_MCHP_PFSOC_DDR_CFG); 168 169 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 170 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 171 172 object_initialize_child(obj, "sd-controller", &s->sdhci, 173 TYPE_CADENCE_SDHCI); 174 175 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 176 } 177 178 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 179 { 180 MachineState *ms = MACHINE(qdev_get_machine()); 181 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 182 const MemMapEntry *memmap = microchip_pfsoc_memmap; 183 MemoryRegion *system_memory = get_system_memory(); 184 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 185 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 186 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 187 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 188 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 189 char *plic_hart_config; 190 size_t plic_hart_config_len; 191 NICInfo *nd; 192 int i; 193 194 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 195 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 196 /* 197 * The cluster must be realized after the RISC-V hart array container, 198 * as the container's CPU object is only created on realize, and the 199 * CPU must exist and have been parented into the cluster before the 200 * cluster is realized. 201 */ 202 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 203 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 204 205 /* Reserved Memory at address 0 */ 206 memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 207 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 208 memory_region_add_subregion(system_memory, 209 memmap[MICROCHIP_PFSOC_RSVD0].base, 210 rsvd0_mem); 211 212 /* E51 DTIM */ 213 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 214 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 215 memory_region_add_subregion(system_memory, 216 memmap[MICROCHIP_PFSOC_E51_DTIM].base, 217 e51_dtim_mem); 218 219 /* Bus Error Units */ 220 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 221 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 222 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 223 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 224 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 225 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 226 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 227 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 228 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 229 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 230 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 231 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 232 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 233 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 234 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 235 236 /* CLINT */ 237 sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, 238 memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, 239 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 240 CLINT_TIMEBASE_FREQ, false); 241 242 /* L2 cache controller */ 243 create_unimplemented_device("microchip.pfsoc.l2cc", 244 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 245 246 /* 247 * Add L2-LIM at reset size. 248 * This should be reduced in size as the L2 Cache Controller WayEnable 249 * register is incremented. Unfortunately I don't see a nice (or any) way 250 * to handle reducing or blocking out the L2 LIM while still allowing it 251 * be re returned to all enabled after a reset. For the time being, just 252 * leave it enabled all the time. This won't break anything, but will be 253 * too generous to misbehaving guests. 254 */ 255 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 256 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 257 memory_region_add_subregion(system_memory, 258 memmap[MICROCHIP_PFSOC_L2LIM].base, 259 l2lim_mem); 260 261 /* create PLIC hart topology configuration string */ 262 plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * 263 ms->smp.cpus; 264 plic_hart_config = g_malloc0(plic_hart_config_len); 265 for (i = 0; i < ms->smp.cpus; i++) { 266 if (i != 0) { 267 strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, 268 plic_hart_config_len); 269 } else { 270 strncat(plic_hart_config, "M", plic_hart_config_len); 271 } 272 plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); 273 } 274 275 /* PLIC */ 276 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 277 plic_hart_config, 0, 278 MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 279 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 280 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 281 MICROCHIP_PFSOC_PLIC_PENDING_BASE, 282 MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 283 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 284 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 285 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 286 memmap[MICROCHIP_PFSOC_PLIC].size); 287 g_free(plic_hart_config); 288 289 /* DMA */ 290 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 291 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 292 memmap[MICROCHIP_PFSOC_DMA].base); 293 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 294 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 295 qdev_get_gpio_in(DEVICE(s->plic), 296 MICROCHIP_PFSOC_DMA_IRQ0 + i)); 297 } 298 299 /* SYSREG */ 300 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 301 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 302 memmap[MICROCHIP_PFSOC_SYSREG].base); 303 304 /* MPUCFG */ 305 create_unimplemented_device("microchip.pfsoc.mpucfg", 306 memmap[MICROCHIP_PFSOC_MPUCFG].base, 307 memmap[MICROCHIP_PFSOC_MPUCFG].size); 308 309 /* DDR SGMII PHY */ 310 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 311 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 312 memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 313 314 /* DDR CFG */ 315 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 316 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 317 memmap[MICROCHIP_PFSOC_DDR_CFG].base); 318 319 /* SDHCI */ 320 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 321 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 322 memmap[MICROCHIP_PFSOC_EMMC_SD].base); 323 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 324 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 325 326 /* MMUARTs */ 327 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 328 memmap[MICROCHIP_PFSOC_MMUART0].base, 329 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 330 serial_hd(0)); 331 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 332 memmap[MICROCHIP_PFSOC_MMUART1].base, 333 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 334 serial_hd(1)); 335 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 336 memmap[MICROCHIP_PFSOC_MMUART2].base, 337 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 338 serial_hd(2)); 339 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 340 memmap[MICROCHIP_PFSOC_MMUART3].base, 341 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 342 serial_hd(3)); 343 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 344 memmap[MICROCHIP_PFSOC_MMUART4].base, 345 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 346 serial_hd(4)); 347 348 /* SPI */ 349 create_unimplemented_device("microchip.pfsoc.spi0", 350 memmap[MICROCHIP_PFSOC_SPI0].base, 351 memmap[MICROCHIP_PFSOC_SPI0].size); 352 create_unimplemented_device("microchip.pfsoc.spi1", 353 memmap[MICROCHIP_PFSOC_SPI1].base, 354 memmap[MICROCHIP_PFSOC_SPI1].size); 355 356 /* I2C1 */ 357 create_unimplemented_device("microchip.pfsoc.i2c1", 358 memmap[MICROCHIP_PFSOC_I2C1].base, 359 memmap[MICROCHIP_PFSOC_I2C1].size); 360 361 /* GEMs */ 362 363 nd = &nd_table[0]; 364 if (nd->used) { 365 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 366 qdev_set_nic_properties(DEVICE(&s->gem0), nd); 367 } 368 nd = &nd_table[1]; 369 if (nd->used) { 370 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 371 qdev_set_nic_properties(DEVICE(&s->gem1), nd); 372 } 373 374 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 375 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 376 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 378 memmap[MICROCHIP_PFSOC_GEM0].base); 379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 380 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 381 382 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 383 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 384 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 386 memmap[MICROCHIP_PFSOC_GEM1].base); 387 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 388 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 389 390 /* GPIOs */ 391 create_unimplemented_device("microchip.pfsoc.gpio0", 392 memmap[MICROCHIP_PFSOC_GPIO0].base, 393 memmap[MICROCHIP_PFSOC_GPIO0].size); 394 create_unimplemented_device("microchip.pfsoc.gpio1", 395 memmap[MICROCHIP_PFSOC_GPIO1].base, 396 memmap[MICROCHIP_PFSOC_GPIO1].size); 397 create_unimplemented_device("microchip.pfsoc.gpio2", 398 memmap[MICROCHIP_PFSOC_GPIO2].base, 399 memmap[MICROCHIP_PFSOC_GPIO2].size); 400 401 /* eNVM */ 402 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 403 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 404 &error_fatal); 405 memory_region_add_subregion(system_memory, 406 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 407 envm_data); 408 409 /* IOSCB */ 410 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 411 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 412 memmap[MICROCHIP_PFSOC_IOSCB].base); 413 414 /* QSPI Flash */ 415 memory_region_init_rom(qspi_xip_mem, OBJECT(dev), 416 "microchip.pfsoc.qspi_xip", 417 memmap[MICROCHIP_PFSOC_QSPI_XIP].size, 418 &error_fatal); 419 memory_region_add_subregion(system_memory, 420 memmap[MICROCHIP_PFSOC_QSPI_XIP].base, 421 qspi_xip_mem); 422 } 423 424 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 425 { 426 DeviceClass *dc = DEVICE_CLASS(oc); 427 428 dc->realize = microchip_pfsoc_soc_realize; 429 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 430 dc->user_creatable = false; 431 } 432 433 static const TypeInfo microchip_pfsoc_soc_type_info = { 434 .name = TYPE_MICROCHIP_PFSOC, 435 .parent = TYPE_DEVICE, 436 .instance_size = sizeof(MicrochipPFSoCState), 437 .instance_init = microchip_pfsoc_soc_instance_init, 438 .class_init = microchip_pfsoc_soc_class_init, 439 }; 440 441 static void microchip_pfsoc_soc_register_types(void) 442 { 443 type_register_static(µchip_pfsoc_soc_type_info); 444 } 445 446 type_init(microchip_pfsoc_soc_register_types) 447 448 static void microchip_icicle_kit_machine_init(MachineState *machine) 449 { 450 MachineClass *mc = MACHINE_GET_CLASS(machine); 451 const MemMapEntry *memmap = microchip_pfsoc_memmap; 452 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 453 MemoryRegion *system_memory = get_system_memory(); 454 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 455 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 456 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 457 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 458 uint64_t mem_high_size; 459 DriveInfo *dinfo = drive_get_next(IF_SD); 460 461 /* Sanity check on RAM size */ 462 if (machine->ram_size < mc->default_ram_size) { 463 char *sz = size_to_str(mc->default_ram_size); 464 error_report("Invalid RAM size, should be bigger than %s", sz); 465 g_free(sz); 466 exit(EXIT_FAILURE); 467 } 468 469 /* Initialize SoC */ 470 object_initialize_child(OBJECT(machine), "soc", &s->soc, 471 TYPE_MICROCHIP_PFSOC); 472 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 473 474 /* Register RAM */ 475 memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low", 476 memmap[MICROCHIP_PFSOC_DRAM_LO].size, 477 &error_fatal); 478 memory_region_init_alias(mem_low_alias, NULL, 479 "microchip.icicle.kit.ram_low.alias", 480 mem_low, 0, 481 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size); 482 memory_region_add_subregion(system_memory, 483 memmap[MICROCHIP_PFSOC_DRAM_LO].base, 484 mem_low); 485 memory_region_add_subregion(system_memory, 486 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, 487 mem_low_alias); 488 489 mem_high_size = machine->ram_size - 1 * GiB; 490 491 memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high", 492 mem_high_size, &error_fatal); 493 memory_region_init_alias(mem_high_alias, NULL, 494 "microchip.icicle.kit.ram_high.alias", 495 mem_high, 0, mem_high_size); 496 memory_region_add_subregion(system_memory, 497 memmap[MICROCHIP_PFSOC_DRAM_HI].base, 498 mem_high); 499 memory_region_add_subregion(system_memory, 500 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, 501 mem_high_alias); 502 503 /* Load the firmware */ 504 riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); 505 506 /* Attach an SD card */ 507 if (dinfo) { 508 CadenceSDHCIState *sdhci = &(s->soc.sdhci); 509 DeviceState *card = qdev_new(TYPE_SD_CARD); 510 511 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 512 &error_fatal); 513 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 514 } 515 } 516 517 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 518 { 519 MachineClass *mc = MACHINE_CLASS(oc); 520 521 mc->desc = "Microchip PolarFire SoC Icicle Kit"; 522 mc->init = microchip_icicle_kit_machine_init; 523 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 524 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 525 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 526 mc->default_cpus = mc->min_cpus; 527 528 /* 529 * Map 513 MiB high memory, the mimimum required high memory size, because 530 * HSS will do memory test against the high memory address range regardless 531 * of physical memory installed. 532 * 533 * See memory_tests() in mss_ddr.c in the HSS source code. 534 */ 535 mc->default_ram_size = 1537 * MiB; 536 } 537 538 static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 539 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 540 .parent = TYPE_MACHINE, 541 .class_init = microchip_icicle_kit_machine_class_init, 542 .instance_size = sizeof(MicrochipIcicleKitState), 543 }; 544 545 static void microchip_icicle_kit_machine_init_register_types(void) 546 { 547 type_register_static(µchip_icicle_kit_machine_typeinfo); 548 } 549 550 type_init(microchip_icicle_kit_machine_init_register_types) 551