1 /* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 10 * 11 * 0) CLINT (Core Level Interruptor) 12 * 1) PLIC (Platform Level Interrupt Controller) 13 * 2) eNVM (Embedded Non-Volatile Memory) 14 * 3) MMUARTs (Multi-Mode UART) 15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it 16 * 5) SiFive Platform DMA (Direct Memory Access Controller) 17 * 6) GEM (Gigabit Ethernet MAC Controller) 18 * 7) DMC (DDR Memory Controller) 19 * 8) IOSCB modules 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qemu/units.h" 40 #include "qemu/cutils.h" 41 #include "qapi/error.h" 42 #include "hw/boards.h" 43 #include "hw/loader.h" 44 #include "hw/sysbus.h" 45 #include "chardev/char.h" 46 #include "hw/cpu/cluster.h" 47 #include "target/riscv/cpu.h" 48 #include "hw/misc/unimp.h" 49 #include "hw/riscv/boot.h" 50 #include "hw/riscv/riscv_hart.h" 51 #include "hw/riscv/microchip_pfsoc.h" 52 #include "hw/intc/sifive_clint.h" 53 #include "hw/intc/sifive_plic.h" 54 #include "sysemu/sysemu.h" 55 56 /* 57 * The BIOS image used by this machine is called Hart Software Services (HSS). 58 * See https://github.com/polarfire-soc/hart-software-services 59 */ 60 #define BIOS_FILENAME "hss.bin" 61 #define RESET_VECTOR 0x20220000 62 63 /* CLINT timebase frequency */ 64 #define CLINT_TIMEBASE_FREQ 1000000 65 66 /* GEM version */ 67 #define GEM_REVISION 0x0107010c 68 69 /* 70 * The complete description of the whole PolarFire SoC memory map is scattered 71 * in different documents. There are several places to look at for memory maps: 72 * 73 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 74 * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 75 * https://www.microsemi.com/document-portal/doc_download/ 76 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 77 * describes the whole picture of the PolarFire SoC memory map. 78 * 79 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 80 * https://www.microsemi.com/document-portal/doc_download/ 81 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 82 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 83 * describes the complete integrated peripherals memory map 84 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 85 * describes the complete IOSCB modules memory maps 86 */ 87 static const MemMapEntry microchip_pfsoc_memmap[] = { 88 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 89 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 90 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 91 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 92 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 93 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 94 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 95 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 96 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 97 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 98 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 99 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 100 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 101 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 102 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 103 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 104 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 105 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 106 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 107 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 108 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 109 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 110 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 111 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, 112 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, 113 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, 114 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 115 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 116 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 117 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 118 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 119 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 120 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 121 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, 122 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 123 [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 }, 124 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, 125 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, 126 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, 127 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, 128 }; 129 130 static void microchip_pfsoc_soc_instance_init(Object *obj) 131 { 132 MachineState *ms = MACHINE(qdev_get_machine()); 133 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 134 135 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 136 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 137 138 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 139 TYPE_RISCV_HART_ARRAY); 140 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 141 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 142 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 143 TYPE_RISCV_CPU_SIFIVE_E51); 144 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 145 146 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 147 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 148 149 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 150 TYPE_RISCV_HART_ARRAY); 151 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 152 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 153 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 154 TYPE_RISCV_CPU_SIFIVE_U54); 155 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 156 157 object_initialize_child(obj, "dma-controller", &s->dma, 158 TYPE_SIFIVE_PDMA); 159 160 object_initialize_child(obj, "sysreg", &s->sysreg, 161 TYPE_MCHP_PFSOC_SYSREG); 162 163 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 164 TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 165 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 166 TYPE_MCHP_PFSOC_DDR_CFG); 167 168 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 169 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 170 171 object_initialize_child(obj, "sd-controller", &s->sdhci, 172 TYPE_CADENCE_SDHCI); 173 174 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 175 } 176 177 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 178 { 179 MachineState *ms = MACHINE(qdev_get_machine()); 180 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 181 const MemMapEntry *memmap = microchip_pfsoc_memmap; 182 MemoryRegion *system_memory = get_system_memory(); 183 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 184 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 185 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 186 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 187 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 188 char *plic_hart_config; 189 size_t plic_hart_config_len; 190 NICInfo *nd; 191 int i; 192 193 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 194 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 195 /* 196 * The cluster must be realized after the RISC-V hart array container, 197 * as the container's CPU object is only created on realize, and the 198 * CPU must exist and have been parented into the cluster before the 199 * cluster is realized. 200 */ 201 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 202 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 203 204 /* Reserved Memory at address 0 */ 205 memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 206 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 207 memory_region_add_subregion(system_memory, 208 memmap[MICROCHIP_PFSOC_RSVD0].base, 209 rsvd0_mem); 210 211 /* E51 DTIM */ 212 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 213 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 214 memory_region_add_subregion(system_memory, 215 memmap[MICROCHIP_PFSOC_E51_DTIM].base, 216 e51_dtim_mem); 217 218 /* Bus Error Units */ 219 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 220 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 221 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 222 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 223 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 224 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 225 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 226 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 227 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 228 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 229 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 230 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 231 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 232 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 233 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 234 235 /* CLINT */ 236 sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, 237 memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, 238 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 239 CLINT_TIMEBASE_FREQ, false); 240 241 /* L2 cache controller */ 242 create_unimplemented_device("microchip.pfsoc.l2cc", 243 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 244 245 /* 246 * Add L2-LIM at reset size. 247 * This should be reduced in size as the L2 Cache Controller WayEnable 248 * register is incremented. Unfortunately I don't see a nice (or any) way 249 * to handle reducing or blocking out the L2 LIM while still allowing it 250 * be re returned to all enabled after a reset. For the time being, just 251 * leave it enabled all the time. This won't break anything, but will be 252 * too generous to misbehaving guests. 253 */ 254 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 255 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 256 memory_region_add_subregion(system_memory, 257 memmap[MICROCHIP_PFSOC_L2LIM].base, 258 l2lim_mem); 259 260 /* create PLIC hart topology configuration string */ 261 plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * 262 ms->smp.cpus; 263 plic_hart_config = g_malloc0(plic_hart_config_len); 264 for (i = 0; i < ms->smp.cpus; i++) { 265 if (i != 0) { 266 strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, 267 plic_hart_config_len); 268 } else { 269 strncat(plic_hart_config, "M", plic_hart_config_len); 270 } 271 plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); 272 } 273 274 /* PLIC */ 275 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 276 plic_hart_config, 0, 277 MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 278 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 279 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 280 MICROCHIP_PFSOC_PLIC_PENDING_BASE, 281 MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 282 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 283 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 284 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 285 memmap[MICROCHIP_PFSOC_PLIC].size); 286 g_free(plic_hart_config); 287 288 /* DMA */ 289 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 290 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 291 memmap[MICROCHIP_PFSOC_DMA].base); 292 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 293 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 294 qdev_get_gpio_in(DEVICE(s->plic), 295 MICROCHIP_PFSOC_DMA_IRQ0 + i)); 296 } 297 298 /* SYSREG */ 299 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 300 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 301 memmap[MICROCHIP_PFSOC_SYSREG].base); 302 303 /* MPUCFG */ 304 create_unimplemented_device("microchip.pfsoc.mpucfg", 305 memmap[MICROCHIP_PFSOC_MPUCFG].base, 306 memmap[MICROCHIP_PFSOC_MPUCFG].size); 307 308 /* DDR SGMII PHY */ 309 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 311 memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 312 313 /* DDR CFG */ 314 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 315 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 316 memmap[MICROCHIP_PFSOC_DDR_CFG].base); 317 318 /* SDHCI */ 319 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 320 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 321 memmap[MICROCHIP_PFSOC_EMMC_SD].base); 322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 323 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 324 325 /* MMUARTs */ 326 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 327 memmap[MICROCHIP_PFSOC_MMUART0].base, 328 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 329 serial_hd(0)); 330 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 331 memmap[MICROCHIP_PFSOC_MMUART1].base, 332 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 333 serial_hd(1)); 334 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 335 memmap[MICROCHIP_PFSOC_MMUART2].base, 336 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 337 serial_hd(2)); 338 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 339 memmap[MICROCHIP_PFSOC_MMUART3].base, 340 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 341 serial_hd(3)); 342 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 343 memmap[MICROCHIP_PFSOC_MMUART4].base, 344 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 345 serial_hd(4)); 346 347 /* SPI */ 348 create_unimplemented_device("microchip.pfsoc.spi0", 349 memmap[MICROCHIP_PFSOC_SPI0].base, 350 memmap[MICROCHIP_PFSOC_SPI0].size); 351 create_unimplemented_device("microchip.pfsoc.spi1", 352 memmap[MICROCHIP_PFSOC_SPI1].base, 353 memmap[MICROCHIP_PFSOC_SPI1].size); 354 355 /* I2C1 */ 356 create_unimplemented_device("microchip.pfsoc.i2c1", 357 memmap[MICROCHIP_PFSOC_I2C1].base, 358 memmap[MICROCHIP_PFSOC_I2C1].size); 359 360 /* GEMs */ 361 362 nd = &nd_table[0]; 363 if (nd->used) { 364 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 365 qdev_set_nic_properties(DEVICE(&s->gem0), nd); 366 } 367 nd = &nd_table[1]; 368 if (nd->used) { 369 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 370 qdev_set_nic_properties(DEVICE(&s->gem1), nd); 371 } 372 373 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 374 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 375 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 377 memmap[MICROCHIP_PFSOC_GEM0].base); 378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 379 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 380 381 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 382 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 383 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 384 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 385 memmap[MICROCHIP_PFSOC_GEM1].base); 386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 387 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 388 389 /* GPIOs */ 390 create_unimplemented_device("microchip.pfsoc.gpio0", 391 memmap[MICROCHIP_PFSOC_GPIO0].base, 392 memmap[MICROCHIP_PFSOC_GPIO0].size); 393 create_unimplemented_device("microchip.pfsoc.gpio1", 394 memmap[MICROCHIP_PFSOC_GPIO1].base, 395 memmap[MICROCHIP_PFSOC_GPIO1].size); 396 create_unimplemented_device("microchip.pfsoc.gpio2", 397 memmap[MICROCHIP_PFSOC_GPIO2].base, 398 memmap[MICROCHIP_PFSOC_GPIO2].size); 399 400 /* eNVM */ 401 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 402 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 403 &error_fatal); 404 memory_region_add_subregion(system_memory, 405 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 406 envm_data); 407 408 /* IOSCB */ 409 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 411 memmap[MICROCHIP_PFSOC_IOSCB].base); 412 413 /* eMMC/SD mux */ 414 create_unimplemented_device("microchip.pfsoc.emmc_sd_mux", 415 memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base, 416 memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size); 417 418 /* QSPI Flash */ 419 memory_region_init_rom(qspi_xip_mem, OBJECT(dev), 420 "microchip.pfsoc.qspi_xip", 421 memmap[MICROCHIP_PFSOC_QSPI_XIP].size, 422 &error_fatal); 423 memory_region_add_subregion(system_memory, 424 memmap[MICROCHIP_PFSOC_QSPI_XIP].base, 425 qspi_xip_mem); 426 } 427 428 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 429 { 430 DeviceClass *dc = DEVICE_CLASS(oc); 431 432 dc->realize = microchip_pfsoc_soc_realize; 433 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 434 dc->user_creatable = false; 435 } 436 437 static const TypeInfo microchip_pfsoc_soc_type_info = { 438 .name = TYPE_MICROCHIP_PFSOC, 439 .parent = TYPE_DEVICE, 440 .instance_size = sizeof(MicrochipPFSoCState), 441 .instance_init = microchip_pfsoc_soc_instance_init, 442 .class_init = microchip_pfsoc_soc_class_init, 443 }; 444 445 static void microchip_pfsoc_soc_register_types(void) 446 { 447 type_register_static(µchip_pfsoc_soc_type_info); 448 } 449 450 type_init(microchip_pfsoc_soc_register_types) 451 452 static void microchip_icicle_kit_machine_init(MachineState *machine) 453 { 454 MachineClass *mc = MACHINE_GET_CLASS(machine); 455 const MemMapEntry *memmap = microchip_pfsoc_memmap; 456 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 457 MemoryRegion *system_memory = get_system_memory(); 458 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 459 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 460 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 461 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 462 uint64_t mem_high_size; 463 DriveInfo *dinfo = drive_get_next(IF_SD); 464 465 /* Sanity check on RAM size */ 466 if (machine->ram_size < mc->default_ram_size) { 467 char *sz = size_to_str(mc->default_ram_size); 468 error_report("Invalid RAM size, should be bigger than %s", sz); 469 g_free(sz); 470 exit(EXIT_FAILURE); 471 } 472 473 /* Initialize SoC */ 474 object_initialize_child(OBJECT(machine), "soc", &s->soc, 475 TYPE_MICROCHIP_PFSOC); 476 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 477 478 /* Register RAM */ 479 memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low", 480 memmap[MICROCHIP_PFSOC_DRAM_LO].size, 481 &error_fatal); 482 memory_region_init_alias(mem_low_alias, NULL, 483 "microchip.icicle.kit.ram_low.alias", 484 mem_low, 0, 485 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size); 486 memory_region_add_subregion(system_memory, 487 memmap[MICROCHIP_PFSOC_DRAM_LO].base, 488 mem_low); 489 memory_region_add_subregion(system_memory, 490 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, 491 mem_low_alias); 492 493 mem_high_size = machine->ram_size - 1 * GiB; 494 495 memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high", 496 mem_high_size, &error_fatal); 497 memory_region_init_alias(mem_high_alias, NULL, 498 "microchip.icicle.kit.ram_high.alias", 499 mem_high, 0, mem_high_size); 500 memory_region_add_subregion(system_memory, 501 memmap[MICROCHIP_PFSOC_DRAM_HI].base, 502 mem_high); 503 memory_region_add_subregion(system_memory, 504 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, 505 mem_high_alias); 506 507 /* Load the firmware */ 508 riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); 509 510 /* Attach an SD card */ 511 if (dinfo) { 512 CadenceSDHCIState *sdhci = &(s->soc.sdhci); 513 DeviceState *card = qdev_new(TYPE_SD_CARD); 514 515 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 516 &error_fatal); 517 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 518 } 519 } 520 521 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 522 { 523 MachineClass *mc = MACHINE_CLASS(oc); 524 525 mc->desc = "Microchip PolarFire SoC Icicle Kit"; 526 mc->init = microchip_icicle_kit_machine_init; 527 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 528 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 529 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 530 mc->default_cpus = mc->min_cpus; 531 532 /* 533 * Map 513 MiB high memory, the mimimum required high memory size, because 534 * HSS will do memory test against the high memory address range regardless 535 * of physical memory installed. 536 * 537 * See memory_tests() in mss_ddr.c in the HSS source code. 538 */ 539 mc->default_ram_size = 1537 * MiB; 540 } 541 542 static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 543 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 544 .parent = TYPE_MACHINE, 545 .class_init = microchip_icicle_kit_machine_class_init, 546 .instance_size = sizeof(MicrochipIcicleKitState), 547 }; 548 549 static void microchip_icicle_kit_machine_init_register_types(void) 550 { 551 type_register_static(µchip_icicle_kit_machine_typeinfo); 552 } 553 554 type_init(microchip_icicle_kit_machine_init_register_types) 555