1 /* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 10 * 11 * 0) CLINT (Core Level Interruptor) 12 * 1) PLIC (Platform Level Interrupt Controller) 13 * 2) eNVM (Embedded Non-Volatile Memory) 14 * 3) MMUARTs (Multi-Mode UART) 15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it 16 * 5) SiFive Platform DMA (Direct Memory Access Controller) 17 * 6) GEM (Gigabit Ethernet MAC Controller) 18 * 7) DMC (DDR Memory Controller) 19 * 8) IOSCB modules 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qemu/units.h" 40 #include "qemu/cutils.h" 41 #include "qapi/error.h" 42 #include "hw/boards.h" 43 #include "hw/loader.h" 44 #include "hw/sysbus.h" 45 #include "chardev/char.h" 46 #include "hw/cpu/cluster.h" 47 #include "target/riscv/cpu.h" 48 #include "hw/misc/unimp.h" 49 #include "hw/riscv/boot.h" 50 #include "hw/riscv/riscv_hart.h" 51 #include "hw/riscv/microchip_pfsoc.h" 52 #include "hw/intc/riscv_aclint.h" 53 #include "hw/intc/sifive_plic.h" 54 #include "sysemu/device_tree.h" 55 #include "sysemu/sysemu.h" 56 57 /* 58 * The BIOS image used by this machine is called Hart Software Services (HSS). 59 * See https://github.com/polarfire-soc/hart-software-services 60 */ 61 #define BIOS_FILENAME "hss.bin" 62 #define RESET_VECTOR 0x20220000 63 64 /* CLINT timebase frequency */ 65 #define CLINT_TIMEBASE_FREQ 1000000 66 67 /* GEM version */ 68 #define GEM_REVISION 0x0107010c 69 70 /* 71 * The complete description of the whole PolarFire SoC memory map is scattered 72 * in different documents. There are several places to look at for memory maps: 73 * 74 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 75 * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 76 * https://www.microsemi.com/document-portal/doc_download/ 77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 78 * describes the whole picture of the PolarFire SoC memory map. 79 * 80 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 81 * https://www.microsemi.com/document-portal/doc_download/ 82 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 83 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 84 * describes the complete integrated peripherals memory map 85 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 86 * describes the complete IOSCB modules memory maps 87 */ 88 static const MemMapEntry microchip_pfsoc_memmap[] = { 89 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 90 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 91 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 92 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 93 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 94 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 95 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 96 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 97 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 98 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 99 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 100 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 101 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 102 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 103 [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, 104 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 105 [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, 106 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 107 [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, 108 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 109 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 110 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 111 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 112 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 113 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 114 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 115 [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, 116 [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, 117 [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, 118 [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, 119 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, 120 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, 121 [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, 122 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, 123 [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, 124 [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, 125 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 126 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 127 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 128 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 129 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 130 [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, 131 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 132 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 133 [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, 134 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, 135 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 136 [MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 }, 137 [MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 }, 138 [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, 139 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, 140 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, 141 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, 142 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, 143 144 }; 145 146 static void microchip_pfsoc_soc_instance_init(Object *obj) 147 { 148 MachineState *ms = MACHINE(qdev_get_machine()); 149 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 150 151 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 152 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 153 154 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 155 TYPE_RISCV_HART_ARRAY); 156 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 157 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 158 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 159 TYPE_RISCV_CPU_SIFIVE_E51); 160 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 161 162 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 163 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 164 165 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 166 TYPE_RISCV_HART_ARRAY); 167 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 168 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 169 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 170 TYPE_RISCV_CPU_SIFIVE_U54); 171 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 172 173 object_initialize_child(obj, "dma-controller", &s->dma, 174 TYPE_SIFIVE_PDMA); 175 176 object_initialize_child(obj, "sysreg", &s->sysreg, 177 TYPE_MCHP_PFSOC_SYSREG); 178 179 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 180 TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 181 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 182 TYPE_MCHP_PFSOC_DDR_CFG); 183 184 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 185 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 186 187 object_initialize_child(obj, "sd-controller", &s->sdhci, 188 TYPE_CADENCE_SDHCI); 189 190 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 191 } 192 193 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 194 { 195 MachineState *ms = MACHINE(qdev_get_machine()); 196 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 197 const MemMapEntry *memmap = microchip_pfsoc_memmap; 198 MemoryRegion *system_memory = get_system_memory(); 199 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 200 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 201 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 202 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 203 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 204 char *plic_hart_config; 205 int i; 206 207 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 208 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 209 /* 210 * The cluster must be realized after the RISC-V hart array container, 211 * as the container's CPU object is only created on realize, and the 212 * CPU must exist and have been parented into the cluster before the 213 * cluster is realized. 214 */ 215 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 216 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 217 218 /* Reserved Memory at address 0 */ 219 memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 220 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 221 memory_region_add_subregion(system_memory, 222 memmap[MICROCHIP_PFSOC_RSVD0].base, 223 rsvd0_mem); 224 225 /* E51 DTIM */ 226 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 227 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 228 memory_region_add_subregion(system_memory, 229 memmap[MICROCHIP_PFSOC_E51_DTIM].base, 230 e51_dtim_mem); 231 232 /* Bus Error Units */ 233 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 234 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 235 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 236 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 237 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 238 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 239 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 240 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 241 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 242 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 243 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 244 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 245 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 246 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 247 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 248 249 /* CLINT */ 250 riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base, 251 0, ms->smp.cpus, false); 252 riscv_aclint_mtimer_create( 253 memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, 254 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 255 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 256 CLINT_TIMEBASE_FREQ, false); 257 258 /* L2 cache controller */ 259 create_unimplemented_device("microchip.pfsoc.l2cc", 260 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 261 262 /* 263 * Add L2-LIM at reset size. 264 * This should be reduced in size as the L2 Cache Controller WayEnable 265 * register is incremented. Unfortunately I don't see a nice (or any) way 266 * to handle reducing or blocking out the L2 LIM while still allowing it 267 * be re returned to all enabled after a reset. For the time being, just 268 * leave it enabled all the time. This won't break anything, but will be 269 * too generous to misbehaving guests. 270 */ 271 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 272 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 273 memory_region_add_subregion(system_memory, 274 memmap[MICROCHIP_PFSOC_L2LIM].base, 275 l2lim_mem); 276 277 /* create PLIC hart topology configuration string */ 278 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); 279 280 /* PLIC */ 281 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 282 plic_hart_config, ms->smp.cpus, 0, 283 MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 284 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 285 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 286 MICROCHIP_PFSOC_PLIC_PENDING_BASE, 287 MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 288 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 289 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 290 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 291 memmap[MICROCHIP_PFSOC_PLIC].size); 292 g_free(plic_hart_config); 293 294 /* DMA */ 295 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 297 memmap[MICROCHIP_PFSOC_DMA].base); 298 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 300 qdev_get_gpio_in(DEVICE(s->plic), 301 MICROCHIP_PFSOC_DMA_IRQ0 + i)); 302 } 303 304 /* SYSREG */ 305 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 307 memmap[MICROCHIP_PFSOC_SYSREG].base); 308 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, 309 qdev_get_gpio_in(DEVICE(s->plic), 310 MICROCHIP_PFSOC_MAILBOX_IRQ)); 311 312 /* AXISW */ 313 create_unimplemented_device("microchip.pfsoc.axisw", 314 memmap[MICROCHIP_PFSOC_AXISW].base, 315 memmap[MICROCHIP_PFSOC_AXISW].size); 316 317 /* MPUCFG */ 318 create_unimplemented_device("microchip.pfsoc.mpucfg", 319 memmap[MICROCHIP_PFSOC_MPUCFG].base, 320 memmap[MICROCHIP_PFSOC_MPUCFG].size); 321 322 /* FMETER */ 323 create_unimplemented_device("microchip.pfsoc.fmeter", 324 memmap[MICROCHIP_PFSOC_FMETER].base, 325 memmap[MICROCHIP_PFSOC_FMETER].size); 326 327 /* DDR SGMII PHY */ 328 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 330 memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 331 332 /* DDR CFG */ 333 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 335 memmap[MICROCHIP_PFSOC_DDR_CFG].base); 336 337 /* SDHCI */ 338 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 340 memmap[MICROCHIP_PFSOC_EMMC_SD].base); 341 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 342 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 343 344 /* MMUARTs */ 345 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 346 memmap[MICROCHIP_PFSOC_MMUART0].base, 347 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 348 serial_hd(0)); 349 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 350 memmap[MICROCHIP_PFSOC_MMUART1].base, 351 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 352 serial_hd(1)); 353 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 354 memmap[MICROCHIP_PFSOC_MMUART2].base, 355 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 356 serial_hd(2)); 357 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 358 memmap[MICROCHIP_PFSOC_MMUART3].base, 359 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 360 serial_hd(3)); 361 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 362 memmap[MICROCHIP_PFSOC_MMUART4].base, 363 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 364 serial_hd(4)); 365 366 /* Watchdogs */ 367 create_unimplemented_device("microchip.pfsoc.watchdog0", 368 memmap[MICROCHIP_PFSOC_WDOG0].base, 369 memmap[MICROCHIP_PFSOC_WDOG0].size); 370 create_unimplemented_device("microchip.pfsoc.watchdog1", 371 memmap[MICROCHIP_PFSOC_WDOG1].base, 372 memmap[MICROCHIP_PFSOC_WDOG1].size); 373 create_unimplemented_device("microchip.pfsoc.watchdog2", 374 memmap[MICROCHIP_PFSOC_WDOG2].base, 375 memmap[MICROCHIP_PFSOC_WDOG2].size); 376 create_unimplemented_device("microchip.pfsoc.watchdog3", 377 memmap[MICROCHIP_PFSOC_WDOG3].base, 378 memmap[MICROCHIP_PFSOC_WDOG3].size); 379 create_unimplemented_device("microchip.pfsoc.watchdog4", 380 memmap[MICROCHIP_PFSOC_WDOG4].base, 381 memmap[MICROCHIP_PFSOC_WDOG4].size); 382 383 /* SPI */ 384 create_unimplemented_device("microchip.pfsoc.spi0", 385 memmap[MICROCHIP_PFSOC_SPI0].base, 386 memmap[MICROCHIP_PFSOC_SPI0].size); 387 create_unimplemented_device("microchip.pfsoc.spi1", 388 memmap[MICROCHIP_PFSOC_SPI1].base, 389 memmap[MICROCHIP_PFSOC_SPI1].size); 390 391 /* I2C */ 392 create_unimplemented_device("microchip.pfsoc.i2c0", 393 memmap[MICROCHIP_PFSOC_I2C0].base, 394 memmap[MICROCHIP_PFSOC_I2C0].size); 395 create_unimplemented_device("microchip.pfsoc.i2c1", 396 memmap[MICROCHIP_PFSOC_I2C1].base, 397 memmap[MICROCHIP_PFSOC_I2C1].size); 398 399 /* CAN */ 400 create_unimplemented_device("microchip.pfsoc.can0", 401 memmap[MICROCHIP_PFSOC_CAN0].base, 402 memmap[MICROCHIP_PFSOC_CAN0].size); 403 create_unimplemented_device("microchip.pfsoc.can1", 404 memmap[MICROCHIP_PFSOC_CAN1].base, 405 memmap[MICROCHIP_PFSOC_CAN1].size); 406 407 /* USB */ 408 create_unimplemented_device("microchip.pfsoc.usb", 409 memmap[MICROCHIP_PFSOC_USB].base, 410 memmap[MICROCHIP_PFSOC_USB].size); 411 412 /* GEMs */ 413 qemu_configure_nic_device(DEVICE(&s->gem0), true, NULL); 414 qemu_configure_nic_device(DEVICE(&s->gem1), true, NULL); 415 416 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 417 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 418 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 420 memmap[MICROCHIP_PFSOC_GEM0].base); 421 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 422 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 423 424 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 425 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 426 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 427 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 428 memmap[MICROCHIP_PFSOC_GEM1].base); 429 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 430 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 431 432 /* GPIOs */ 433 create_unimplemented_device("microchip.pfsoc.gpio0", 434 memmap[MICROCHIP_PFSOC_GPIO0].base, 435 memmap[MICROCHIP_PFSOC_GPIO0].size); 436 create_unimplemented_device("microchip.pfsoc.gpio1", 437 memmap[MICROCHIP_PFSOC_GPIO1].base, 438 memmap[MICROCHIP_PFSOC_GPIO1].size); 439 create_unimplemented_device("microchip.pfsoc.gpio2", 440 memmap[MICROCHIP_PFSOC_GPIO2].base, 441 memmap[MICROCHIP_PFSOC_GPIO2].size); 442 443 /* eNVM */ 444 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 445 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 446 &error_fatal); 447 memory_region_add_subregion(system_memory, 448 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 449 envm_data); 450 451 /* IOSCB */ 452 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 453 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 454 memmap[MICROCHIP_PFSOC_IOSCB].base); 455 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0, 456 qdev_get_gpio_in(DEVICE(s->plic), 457 MICROCHIP_PFSOC_MAILBOX_IRQ)); 458 459 /* FPGA Fabric */ 460 create_unimplemented_device("microchip.pfsoc.fabricfic3", 461 memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base, 462 memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size); 463 /* FPGA Fabric */ 464 create_unimplemented_device("microchip.pfsoc.fabricfic0", 465 memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base, 466 memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size); 467 /* FPGA Fabric */ 468 create_unimplemented_device("microchip.pfsoc.fabricfic1", 469 memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base, 470 memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size); 471 472 /* QSPI Flash */ 473 memory_region_init_rom(qspi_xip_mem, OBJECT(dev), 474 "microchip.pfsoc.qspi_xip", 475 memmap[MICROCHIP_PFSOC_QSPI_XIP].size, 476 &error_fatal); 477 memory_region_add_subregion(system_memory, 478 memmap[MICROCHIP_PFSOC_QSPI_XIP].base, 479 qspi_xip_mem); 480 } 481 482 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 483 { 484 DeviceClass *dc = DEVICE_CLASS(oc); 485 486 dc->realize = microchip_pfsoc_soc_realize; 487 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 488 dc->user_creatable = false; 489 } 490 491 static const TypeInfo microchip_pfsoc_soc_type_info = { 492 .name = TYPE_MICROCHIP_PFSOC, 493 .parent = TYPE_DEVICE, 494 .instance_size = sizeof(MicrochipPFSoCState), 495 .instance_init = microchip_pfsoc_soc_instance_init, 496 .class_init = microchip_pfsoc_soc_class_init, 497 }; 498 499 static void microchip_pfsoc_soc_register_types(void) 500 { 501 type_register_static(µchip_pfsoc_soc_type_info); 502 } 503 504 type_init(microchip_pfsoc_soc_register_types) 505 506 static void microchip_icicle_kit_machine_init(MachineState *machine) 507 { 508 MachineClass *mc = MACHINE_GET_CLASS(machine); 509 const MemMapEntry *memmap = microchip_pfsoc_memmap; 510 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 511 MemoryRegion *system_memory = get_system_memory(); 512 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 513 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 514 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 515 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 516 uint64_t mem_low_size, mem_high_size; 517 hwaddr firmware_load_addr; 518 const char *firmware_name; 519 bool kernel_as_payload = false; 520 target_ulong firmware_end_addr, kernel_start_addr; 521 uint64_t kernel_entry; 522 uint32_t fdt_load_addr; 523 DriveInfo *dinfo = drive_get(IF_SD, 0, 0); 524 525 /* Sanity check on RAM size */ 526 if (machine->ram_size < mc->default_ram_size) { 527 char *sz = size_to_str(mc->default_ram_size); 528 error_report("Invalid RAM size, should be bigger than %s", sz); 529 g_free(sz); 530 exit(EXIT_FAILURE); 531 } 532 533 /* Initialize SoC */ 534 object_initialize_child(OBJECT(machine), "soc", &s->soc, 535 TYPE_MICROCHIP_PFSOC); 536 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 537 538 /* Split RAM into low and high regions using aliases to machine->ram */ 539 mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; 540 mem_high_size = machine->ram_size - mem_low_size; 541 memory_region_init_alias(mem_low, NULL, 542 "microchip.icicle.kit.ram_low", machine->ram, 543 0, mem_low_size); 544 memory_region_init_alias(mem_high, NULL, 545 "microchip.icicle.kit.ram_high", machine->ram, 546 mem_low_size, mem_high_size); 547 548 /* Register RAM */ 549 memory_region_add_subregion(system_memory, 550 memmap[MICROCHIP_PFSOC_DRAM_LO].base, 551 mem_low); 552 memory_region_add_subregion(system_memory, 553 memmap[MICROCHIP_PFSOC_DRAM_HI].base, 554 mem_high); 555 556 /* Create aliases for the low and high RAM regions */ 557 memory_region_init_alias(mem_low_alias, NULL, 558 "microchip.icicle.kit.ram_low.alias", 559 mem_low, 0, mem_low_size); 560 memory_region_add_subregion(system_memory, 561 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, 562 mem_low_alias); 563 memory_region_init_alias(mem_high_alias, NULL, 564 "microchip.icicle.kit.ram_high.alias", 565 mem_high, 0, mem_high_size); 566 memory_region_add_subregion(system_memory, 567 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, 568 mem_high_alias); 569 570 /* Attach an SD card */ 571 if (dinfo) { 572 CadenceSDHCIState *sdhci = &(s->soc.sdhci); 573 DeviceState *card = qdev_new(TYPE_SD_CARD); 574 575 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 576 &error_fatal); 577 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 578 } 579 580 /* 581 * We follow the following table to select which payload we execute. 582 * 583 * -bios | -kernel | payload 584 * -------+------------+-------- 585 * N | N | HSS 586 * Y | don't care | HSS 587 * N | Y | kernel 588 * 589 * This ensures backwards compatibility with how we used to expose -bios 590 * to users but allows them to run through direct kernel booting as well. 591 * 592 * When -kernel is used for direct boot, -dtb must be present to provide 593 * a valid device tree for the board, as we don't generate device tree. 594 */ 595 596 if (machine->kernel_filename && machine->dtb) { 597 int fdt_size; 598 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 599 if (!machine->fdt) { 600 error_report("load_device_tree() failed"); 601 exit(1); 602 } 603 604 firmware_name = RISCV64_BIOS_BIN; 605 firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base; 606 kernel_as_payload = true; 607 } 608 609 if (!kernel_as_payload) { 610 firmware_name = BIOS_FILENAME; 611 firmware_load_addr = RESET_VECTOR; 612 } 613 614 /* Load the firmware */ 615 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 616 firmware_load_addr, NULL); 617 618 if (kernel_as_payload) { 619 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 620 firmware_end_addr); 621 622 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, 623 kernel_start_addr, true, NULL); 624 625 /* Compute the fdt load address in dram */ 626 fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, 627 memmap[MICROCHIP_PFSOC_DRAM_LO].size, 628 machine); 629 riscv_load_fdt(fdt_load_addr, machine->fdt); 630 631 /* Load the reset vector */ 632 riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, 633 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 634 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 635 kernel_entry, fdt_load_addr); 636 } 637 } 638 639 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 640 { 641 MachineClass *mc = MACHINE_CLASS(oc); 642 643 mc->desc = "Microchip PolarFire SoC Icicle Kit"; 644 mc->init = microchip_icicle_kit_machine_init; 645 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 646 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 647 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 648 mc->default_cpus = mc->min_cpus; 649 mc->default_ram_id = "microchip.icicle.kit.ram"; 650 651 /* 652 * Map 513 MiB high memory, the minimum required high memory size, because 653 * HSS will do memory test against the high memory address range regardless 654 * of physical memory installed. 655 * 656 * See memory_tests() in mss_ddr.c in the HSS source code. 657 */ 658 mc->default_ram_size = 1537 * MiB; 659 } 660 661 static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 662 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 663 .parent = TYPE_MACHINE, 664 .class_init = microchip_icicle_kit_machine_class_init, 665 .instance_size = sizeof(MicrochipIcicleKitState), 666 }; 667 668 static void microchip_icicle_kit_machine_init_register_types(void) 669 { 670 type_register_static(µchip_icicle_kit_machine_typeinfo); 671 } 672 673 type_init(microchip_icicle_kit_machine_init_register_types) 674