1 /* 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 10 * 11 * 0) CLINT (Core Level Interruptor) 12 * 1) PLIC (Platform Level Interrupt Controller) 13 * 2) eNVM (Embedded Non-Volatile Memory) 14 * 3) MMUARTs (Multi-Mode UART) 15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it 16 * 5) SiFive Platform DMA (Direct Memory Access Controller) 17 * 6) GEM (Gigabit Ethernet MAC Controller) 18 * 7) DMC (DDR Memory Controller) 19 * 8) IOSCB modules 20 * 21 * This board currently generates devicetree dynamically that indicates at least 22 * two harts and up to five harts. 23 * 24 * This program is free software; you can redistribute it and/or modify it 25 * under the terms and conditions of the GNU General Public License, 26 * version 2 or later, as published by the Free Software Foundation. 27 * 28 * This program is distributed in the hope it will be useful, but WITHOUT 29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 30 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 31 * more details. 32 * 33 * You should have received a copy of the GNU General Public License along with 34 * this program. If not, see <http://www.gnu.org/licenses/>. 35 */ 36 37 #include "qemu/osdep.h" 38 #include "qemu/error-report.h" 39 #include "qemu/log.h" 40 #include "qemu/units.h" 41 #include "qemu/cutils.h" 42 #include "qapi/error.h" 43 #include "hw/boards.h" 44 #include "hw/irq.h" 45 #include "hw/loader.h" 46 #include "hw/sysbus.h" 47 #include "chardev/char.h" 48 #include "hw/cpu/cluster.h" 49 #include "target/riscv/cpu.h" 50 #include "hw/misc/unimp.h" 51 #include "hw/riscv/boot.h" 52 #include "hw/riscv/riscv_hart.h" 53 #include "hw/riscv/microchip_pfsoc.h" 54 #include "hw/intc/sifive_clint.h" 55 #include "hw/intc/sifive_plic.h" 56 #include "sysemu/sysemu.h" 57 58 /* 59 * The BIOS image used by this machine is called Hart Software Services (HSS). 60 * See https://github.com/polarfire-soc/hart-software-services 61 */ 62 #define BIOS_FILENAME "hss.bin" 63 #define RESET_VECTOR 0x20220000 64 65 /* CLINT timebase frequency */ 66 #define CLINT_TIMEBASE_FREQ 1000000 67 68 /* GEM version */ 69 #define GEM_REVISION 0x0107010c 70 71 /* 72 * The complete description of the whole PolarFire SoC memory map is scattered 73 * in different documents. There are several places to look at for memory maps: 74 * 75 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 76 * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 77 * https://www.microsemi.com/document-portal/doc_download/ 78 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 79 * describes the whole picture of the PolarFire SoC memory map. 80 * 81 * 2 A zip file for PolarFire soC memory map, which can be downloaded from 82 * https://www.microsemi.com/document-portal/doc_download/ 83 * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 84 * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 85 * describes the complete integrated peripherals memory map 86 * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 87 * describes the complete IOSCB modules memory maps 88 */ 89 static const MemMapEntry microchip_pfsoc_memmap[] = { 90 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 91 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 92 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 93 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 94 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 95 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 96 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 97 [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 98 [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 99 [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 100 [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 101 [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 102 [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 103 [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 104 [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 105 [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 106 [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 107 [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 108 [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 109 [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 110 [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 111 [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 112 [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 113 [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, 114 [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, 115 [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, 116 [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 117 [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 118 [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 119 [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 120 [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 121 [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 122 [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 123 [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, 124 [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 125 [MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 }, 126 [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, 127 [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, 128 [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, 129 [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, 130 }; 131 132 static void microchip_pfsoc_soc_instance_init(Object *obj) 133 { 134 MachineState *ms = MACHINE(qdev_get_machine()); 135 MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 136 137 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 138 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 139 140 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 141 TYPE_RISCV_HART_ARRAY); 142 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 143 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 144 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 145 TYPE_RISCV_CPU_SIFIVE_E51); 146 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 147 148 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 149 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 150 151 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 152 TYPE_RISCV_HART_ARRAY); 153 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 154 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 155 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 156 TYPE_RISCV_CPU_SIFIVE_U54); 157 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 158 159 object_initialize_child(obj, "dma-controller", &s->dma, 160 TYPE_SIFIVE_PDMA); 161 162 object_initialize_child(obj, "sysreg", &s->sysreg, 163 TYPE_MCHP_PFSOC_SYSREG); 164 165 object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 166 TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 167 object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 168 TYPE_MCHP_PFSOC_DDR_CFG); 169 170 object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 171 object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 172 173 object_initialize_child(obj, "sd-controller", &s->sdhci, 174 TYPE_CADENCE_SDHCI); 175 176 object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 177 } 178 179 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 180 { 181 MachineState *ms = MACHINE(qdev_get_machine()); 182 MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 183 const MemMapEntry *memmap = microchip_pfsoc_memmap; 184 MemoryRegion *system_memory = get_system_memory(); 185 MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 186 MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 187 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 188 MemoryRegion *envm_data = g_new(MemoryRegion, 1); 189 MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 190 char *plic_hart_config; 191 size_t plic_hart_config_len; 192 NICInfo *nd; 193 int i; 194 195 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 196 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 197 /* 198 * The cluster must be realized after the RISC-V hart array container, 199 * as the container's CPU object is only created on realize, and the 200 * CPU must exist and have been parented into the cluster before the 201 * cluster is realized. 202 */ 203 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 204 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 205 206 /* Reserved Memory at address 0 */ 207 memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 208 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 209 memory_region_add_subregion(system_memory, 210 memmap[MICROCHIP_PFSOC_RSVD0].base, 211 rsvd0_mem); 212 213 /* E51 DTIM */ 214 memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 215 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 216 memory_region_add_subregion(system_memory, 217 memmap[MICROCHIP_PFSOC_E51_DTIM].base, 218 e51_dtim_mem); 219 220 /* Bus Error Units */ 221 create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 222 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 223 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 224 create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 225 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 226 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 227 create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 228 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 229 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 230 create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 231 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 232 memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 233 create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 234 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 235 memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 236 237 /* CLINT */ 238 sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, 239 memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, 240 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 241 CLINT_TIMEBASE_FREQ, false); 242 243 /* L2 cache controller */ 244 create_unimplemented_device("microchip.pfsoc.l2cc", 245 memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 246 247 /* 248 * Add L2-LIM at reset size. 249 * This should be reduced in size as the L2 Cache Controller WayEnable 250 * register is incremented. Unfortunately I don't see a nice (or any) way 251 * to handle reducing or blocking out the L2 LIM while still allowing it 252 * be re returned to all enabled after a reset. For the time being, just 253 * leave it enabled all the time. This won't break anything, but will be 254 * too generous to misbehaving guests. 255 */ 256 memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 257 memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 258 memory_region_add_subregion(system_memory, 259 memmap[MICROCHIP_PFSOC_L2LIM].base, 260 l2lim_mem); 261 262 /* create PLIC hart topology configuration string */ 263 plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * 264 ms->smp.cpus; 265 plic_hart_config = g_malloc0(plic_hart_config_len); 266 for (i = 0; i < ms->smp.cpus; i++) { 267 if (i != 0) { 268 strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, 269 plic_hart_config_len); 270 } else { 271 strncat(plic_hart_config, "M", plic_hart_config_len); 272 } 273 plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); 274 } 275 276 /* PLIC */ 277 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 278 plic_hart_config, 0, 279 MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 280 MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 281 MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 282 MICROCHIP_PFSOC_PLIC_PENDING_BASE, 283 MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 284 MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 285 MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 286 MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 287 memmap[MICROCHIP_PFSOC_PLIC].size); 288 g_free(plic_hart_config); 289 290 /* DMA */ 291 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 292 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 293 memmap[MICROCHIP_PFSOC_DMA].base); 294 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 295 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 296 qdev_get_gpio_in(DEVICE(s->plic), 297 MICROCHIP_PFSOC_DMA_IRQ0 + i)); 298 } 299 300 /* SYSREG */ 301 sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 303 memmap[MICROCHIP_PFSOC_SYSREG].base); 304 305 /* MPUCFG */ 306 create_unimplemented_device("microchip.pfsoc.mpucfg", 307 memmap[MICROCHIP_PFSOC_MPUCFG].base, 308 memmap[MICROCHIP_PFSOC_MPUCFG].size); 309 310 /* DDR SGMII PHY */ 311 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 312 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 313 memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 314 315 /* DDR CFG */ 316 sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 317 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 318 memmap[MICROCHIP_PFSOC_DDR_CFG].base); 319 320 /* SDHCI */ 321 sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 322 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 323 memmap[MICROCHIP_PFSOC_EMMC_SD].base); 324 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 325 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 326 327 /* MMUARTs */ 328 s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 329 memmap[MICROCHIP_PFSOC_MMUART0].base, 330 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 331 serial_hd(0)); 332 s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 333 memmap[MICROCHIP_PFSOC_MMUART1].base, 334 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 335 serial_hd(1)); 336 s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 337 memmap[MICROCHIP_PFSOC_MMUART2].base, 338 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 339 serial_hd(2)); 340 s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 341 memmap[MICROCHIP_PFSOC_MMUART3].base, 342 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 343 serial_hd(3)); 344 s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 345 memmap[MICROCHIP_PFSOC_MMUART4].base, 346 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 347 serial_hd(4)); 348 349 /* SPI */ 350 create_unimplemented_device("microchip.pfsoc.spi0", 351 memmap[MICROCHIP_PFSOC_SPI0].base, 352 memmap[MICROCHIP_PFSOC_SPI0].size); 353 create_unimplemented_device("microchip.pfsoc.spi1", 354 memmap[MICROCHIP_PFSOC_SPI1].base, 355 memmap[MICROCHIP_PFSOC_SPI1].size); 356 357 /* I2C1 */ 358 create_unimplemented_device("microchip.pfsoc.i2c1", 359 memmap[MICROCHIP_PFSOC_I2C1].base, 360 memmap[MICROCHIP_PFSOC_I2C1].size); 361 362 /* GEMs */ 363 364 nd = &nd_table[0]; 365 if (nd->used) { 366 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 367 qdev_set_nic_properties(DEVICE(&s->gem0), nd); 368 } 369 nd = &nd_table[1]; 370 if (nd->used) { 371 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 372 qdev_set_nic_properties(DEVICE(&s->gem1), nd); 373 } 374 375 object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 376 object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 377 sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 379 memmap[MICROCHIP_PFSOC_GEM0].base); 380 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 381 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 382 383 object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 384 object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 385 sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 386 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 387 memmap[MICROCHIP_PFSOC_GEM1].base); 388 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 389 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 390 391 /* GPIOs */ 392 create_unimplemented_device("microchip.pfsoc.gpio0", 393 memmap[MICROCHIP_PFSOC_GPIO0].base, 394 memmap[MICROCHIP_PFSOC_GPIO0].size); 395 create_unimplemented_device("microchip.pfsoc.gpio1", 396 memmap[MICROCHIP_PFSOC_GPIO1].base, 397 memmap[MICROCHIP_PFSOC_GPIO1].size); 398 create_unimplemented_device("microchip.pfsoc.gpio2", 399 memmap[MICROCHIP_PFSOC_GPIO2].base, 400 memmap[MICROCHIP_PFSOC_GPIO2].size); 401 402 /* eNVM */ 403 memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 404 memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 405 &error_fatal); 406 memory_region_add_subregion(system_memory, 407 memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 408 envm_data); 409 410 /* IOSCB */ 411 sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 412 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 413 memmap[MICROCHIP_PFSOC_IOSCB].base); 414 415 /* eMMC/SD mux */ 416 create_unimplemented_device("microchip.pfsoc.emmc_sd_mux", 417 memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base, 418 memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size); 419 420 /* QSPI Flash */ 421 memory_region_init_rom(qspi_xip_mem, OBJECT(dev), 422 "microchip.pfsoc.qspi_xip", 423 memmap[MICROCHIP_PFSOC_QSPI_XIP].size, 424 &error_fatal); 425 memory_region_add_subregion(system_memory, 426 memmap[MICROCHIP_PFSOC_QSPI_XIP].base, 427 qspi_xip_mem); 428 } 429 430 static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 431 { 432 DeviceClass *dc = DEVICE_CLASS(oc); 433 434 dc->realize = microchip_pfsoc_soc_realize; 435 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 436 dc->user_creatable = false; 437 } 438 439 static const TypeInfo microchip_pfsoc_soc_type_info = { 440 .name = TYPE_MICROCHIP_PFSOC, 441 .parent = TYPE_DEVICE, 442 .instance_size = sizeof(MicrochipPFSoCState), 443 .instance_init = microchip_pfsoc_soc_instance_init, 444 .class_init = microchip_pfsoc_soc_class_init, 445 }; 446 447 static void microchip_pfsoc_soc_register_types(void) 448 { 449 type_register_static(µchip_pfsoc_soc_type_info); 450 } 451 452 type_init(microchip_pfsoc_soc_register_types) 453 454 static void microchip_icicle_kit_machine_init(MachineState *machine) 455 { 456 MachineClass *mc = MACHINE_GET_CLASS(machine); 457 const MemMapEntry *memmap = microchip_pfsoc_memmap; 458 MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 459 MemoryRegion *system_memory = get_system_memory(); 460 MemoryRegion *mem_low = g_new(MemoryRegion, 1); 461 MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 462 MemoryRegion *mem_high = g_new(MemoryRegion, 1); 463 MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 464 uint64_t mem_high_size; 465 DriveInfo *dinfo = drive_get_next(IF_SD); 466 467 /* Sanity check on RAM size */ 468 if (machine->ram_size < mc->default_ram_size) { 469 char *sz = size_to_str(mc->default_ram_size); 470 error_report("Invalid RAM size, should be bigger than %s", sz); 471 g_free(sz); 472 exit(EXIT_FAILURE); 473 } 474 475 /* Initialize SoC */ 476 object_initialize_child(OBJECT(machine), "soc", &s->soc, 477 TYPE_MICROCHIP_PFSOC); 478 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 479 480 /* Register RAM */ 481 memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low", 482 memmap[MICROCHIP_PFSOC_DRAM_LO].size, 483 &error_fatal); 484 memory_region_init_alias(mem_low_alias, NULL, 485 "microchip.icicle.kit.ram_low.alias", 486 mem_low, 0, 487 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size); 488 memory_region_add_subregion(system_memory, 489 memmap[MICROCHIP_PFSOC_DRAM_LO].base, 490 mem_low); 491 memory_region_add_subregion(system_memory, 492 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, 493 mem_low_alias); 494 495 mem_high_size = machine->ram_size - 1 * GiB; 496 497 memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high", 498 mem_high_size, &error_fatal); 499 memory_region_init_alias(mem_high_alias, NULL, 500 "microchip.icicle.kit.ram_high.alias", 501 mem_high, 0, mem_high_size); 502 memory_region_add_subregion(system_memory, 503 memmap[MICROCHIP_PFSOC_DRAM_HI].base, 504 mem_high); 505 memory_region_add_subregion(system_memory, 506 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, 507 mem_high_alias); 508 509 /* Load the firmware */ 510 riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); 511 512 /* Attach an SD card */ 513 if (dinfo) { 514 CadenceSDHCIState *sdhci = &(s->soc.sdhci); 515 DeviceState *card = qdev_new(TYPE_SD_CARD); 516 517 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 518 &error_fatal); 519 qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 520 } 521 } 522 523 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 524 { 525 MachineClass *mc = MACHINE_CLASS(oc); 526 527 mc->desc = "Microchip PolarFire SoC Icicle Kit"; 528 mc->init = microchip_icicle_kit_machine_init; 529 mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 530 MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 531 mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 532 mc->default_cpus = mc->min_cpus; 533 534 /* 535 * Map 513 MiB high memory, the mimimum required high memory size, because 536 * HSS will do memory test against the high memory address range regardless 537 * of physical memory installed. 538 * 539 * See memory_tests() in mss_ddr.c in the HSS source code. 540 */ 541 mc->default_ram_size = 1537 * MiB; 542 } 543 544 static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 545 .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 546 .parent = TYPE_MACHINE, 547 .class_init = microchip_icicle_kit_machine_class_init, 548 .instance_size = sizeof(MicrochipIcicleKitState), 549 }; 550 551 static void microchip_icicle_kit_machine_init_register_types(void) 552 { 553 type_register_static(µchip_icicle_kit_machine_typeinfo); 554 } 555 556 type_init(microchip_icicle_kit_machine_init_register_types) 557