xref: /openbmc/qemu/hw/riscv/meson.build (revision c51a3f5d)
1riscv_ss = ss.source_set()
2riscv_ss.add(files('boot.c'), fdt)
3riscv_ss.add(files('numa.c'))
4riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
5riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
6riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
7riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
8riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
9riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
10riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
11riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
12riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
13riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
14riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
15riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
16riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
17riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
18riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
19
20hw_arch += {'riscv': riscv_ss}
21