1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/qtest.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/reset.h" 34 35 #include <libfdt.h> 36 37 bool riscv_is_32bit(RISCVHartArrayState *harts) 38 { 39 return harts->harts[0].env.misa_mxl_max == MXL_RV32; 40 } 41 42 /* 43 * Return the per-socket PLIC hart topology configuration string 44 * (caller must free with g_free()) 45 */ 46 char *riscv_plic_hart_config_string(int hart_count) 47 { 48 g_autofree const char **vals = g_new(const char *, hart_count + 1); 49 int i; 50 51 for (i = 0; i < hart_count; i++) { 52 CPUState *cs = qemu_get_cpu(i); 53 CPURISCVState *env = &RISCV_CPU(cs)->env; 54 55 if (kvm_enabled()) { 56 vals[i] = "S"; 57 } else if (riscv_has_ext(env, RVS)) { 58 vals[i] = "MS"; 59 } else { 60 vals[i] = "M"; 61 } 62 } 63 vals[i] = NULL; 64 65 /* g_strjoinv() obliges us to cast away const here */ 66 return g_strjoinv(",", (char **)vals); 67 } 68 69 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, 70 target_ulong firmware_end_addr) { 71 if (riscv_is_32bit(harts)) { 72 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 73 } else { 74 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 75 } 76 } 77 78 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) 79 { 80 if (riscv_is_32bit(harts)) { 81 return RISCV32_BIOS_BIN; 82 } 83 84 return RISCV64_BIOS_BIN; 85 } 86 87 static char *riscv_find_bios(const char *bios_filename) 88 { 89 char *filename; 90 91 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); 92 if (filename == NULL) { 93 if (!qtest_enabled()) { 94 /* 95 * We only ship OpenSBI binary bios images in the QEMU source. 96 * For machines that use images other than the default bios, 97 * running QEMU test will complain hence let's suppress the error 98 * report for QEMU testing. 99 */ 100 error_report("Unable to find the RISC-V BIOS \"%s\"", 101 bios_filename); 102 exit(1); 103 } 104 } 105 106 return filename; 107 } 108 109 char *riscv_find_firmware(const char *firmware_filename, 110 const char *default_machine_firmware) 111 { 112 char *filename = NULL; 113 114 if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { 115 /* 116 * The user didn't specify -bios, or has specified "-bios default". 117 * That means we are going to load the OpenSBI binary included in 118 * the QEMU source. 119 */ 120 filename = riscv_find_bios(default_machine_firmware); 121 } else if (strcmp(firmware_filename, "none")) { 122 filename = riscv_find_bios(firmware_filename); 123 } 124 125 return filename; 126 } 127 128 target_ulong riscv_find_and_load_firmware(MachineState *machine, 129 const char *default_machine_firmware, 130 hwaddr firmware_load_addr, 131 symbol_fn_t sym_cb) 132 { 133 char *firmware_filename; 134 target_ulong firmware_end_addr = firmware_load_addr; 135 136 firmware_filename = riscv_find_firmware(machine->firmware, 137 default_machine_firmware); 138 139 if (firmware_filename) { 140 /* If not "none" load the firmware */ 141 firmware_end_addr = riscv_load_firmware(firmware_filename, 142 firmware_load_addr, sym_cb); 143 g_free(firmware_filename); 144 } 145 146 return firmware_end_addr; 147 } 148 149 target_ulong riscv_load_firmware(const char *firmware_filename, 150 hwaddr firmware_load_addr, 151 symbol_fn_t sym_cb) 152 { 153 uint64_t firmware_entry, firmware_end; 154 ssize_t firmware_size; 155 156 g_assert(firmware_filename != NULL); 157 158 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 159 &firmware_entry, NULL, &firmware_end, NULL, 160 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 161 return firmware_end; 162 } 163 164 firmware_size = load_image_targphys_as(firmware_filename, 165 firmware_load_addr, 166 current_machine->ram_size, NULL); 167 168 if (firmware_size > 0) { 169 return firmware_load_addr + firmware_size; 170 } 171 172 error_report("could not load firmware '%s'", firmware_filename); 173 exit(1); 174 } 175 176 static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) 177 { 178 const char *filename = machine->initrd_filename; 179 uint64_t mem_size = machine->ram_size; 180 void *fdt = machine->fdt; 181 hwaddr start, end; 182 ssize_t size; 183 184 g_assert(filename != NULL); 185 186 /* 187 * We want to put the initrd far enough into RAM that when the 188 * kernel is uncompressed it will not clobber the initrd. However 189 * on boards without much RAM we must ensure that we still leave 190 * enough room for a decent sized initrd, and on boards with large 191 * amounts of RAM we must avoid the initrd being so far up in RAM 192 * that it is outside lowmem and inaccessible to the kernel. 193 * So for boards with less than 256MB of RAM we put the initrd 194 * halfway into RAM, and for boards with 256MB of RAM or more we put 195 * the initrd at 128MB. 196 */ 197 start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 198 199 size = load_ramdisk(filename, start, mem_size - start); 200 if (size == -1) { 201 size = load_image_targphys(filename, start, mem_size - start); 202 if (size == -1) { 203 error_report("could not load ramdisk '%s'", filename); 204 exit(1); 205 } 206 } 207 208 /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ 209 if (fdt) { 210 end = start + size; 211 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); 212 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); 213 } 214 } 215 216 target_ulong riscv_load_kernel(MachineState *machine, 217 RISCVHartArrayState *harts, 218 target_ulong kernel_start_addr, 219 bool load_initrd, 220 symbol_fn_t sym_cb) 221 { 222 const char *kernel_filename = machine->kernel_filename; 223 uint64_t kernel_load_base, kernel_entry; 224 void *fdt = machine->fdt; 225 226 g_assert(kernel_filename != NULL); 227 228 /* 229 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 230 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 231 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 232 * the (expected) load address load address. This allows kernels to have 233 * separate SBI and ELF entry points (used by FreeBSD, for example). 234 */ 235 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 236 NULL, &kernel_load_base, NULL, NULL, 0, 237 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 238 kernel_entry = kernel_load_base; 239 goto out; 240 } 241 242 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 243 NULL, NULL, NULL) > 0) { 244 goto out; 245 } 246 247 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 248 current_machine->ram_size, NULL) > 0) { 249 kernel_entry = kernel_start_addr; 250 goto out; 251 } 252 253 error_report("could not load kernel '%s'", kernel_filename); 254 exit(1); 255 256 out: 257 /* 258 * For 32 bit CPUs 'kernel_entry' can be sign-extended by 259 * load_elf_ram_sym(). 260 */ 261 if (riscv_is_32bit(harts)) { 262 kernel_entry = extract64(kernel_entry, 0, 32); 263 } 264 265 if (load_initrd && machine->initrd_filename) { 266 riscv_load_initrd(machine, kernel_entry); 267 } 268 269 if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { 270 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 271 machine->kernel_cmdline); 272 } 273 274 return kernel_entry; 275 } 276 277 /* 278 * This function makes an assumption that the DRAM interval 279 * 'dram_base' + 'dram_size' is contiguous. 280 * 281 * Considering that 'dram_end' is the lowest value between 282 * the end of the DRAM block and MachineState->ram_size, the 283 * FDT location will vary according to 'dram_base': 284 * 285 * - if 'dram_base' is less that 3072 MiB, the FDT will be 286 * put at the lowest value between 3072 MiB and 'dram_end'; 287 * 288 * - if 'dram_base' is higher than 3072 MiB, the FDT will be 289 * put at 'dram_end'. 290 * 291 * The FDT is fdt_packed() during the calculation. 292 */ 293 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, 294 MachineState *ms) 295 { 296 int ret = fdt_pack(ms->fdt); 297 hwaddr dram_end, temp; 298 int fdtsize; 299 300 /* Should only fail if we've built a corrupted tree */ 301 g_assert(ret == 0); 302 303 fdtsize = fdt_totalsize(ms->fdt); 304 if (fdtsize <= 0) { 305 error_report("invalid device-tree"); 306 exit(1); 307 } 308 309 /* 310 * A dram_size == 0, usually from a MemMapEntry[].size element, 311 * means that the DRAM block goes all the way to ms->ram_size. 312 */ 313 dram_end = dram_base; 314 dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size; 315 316 /* 317 * We should put fdt as far as possible to avoid kernel/initrd overwriting 318 * its content. But it should be addressable by 32 bit system as well. 319 * Thus, put it at an 2MB aligned address that less than fdt size from the 320 * end of dram or 3GB whichever is lesser. 321 */ 322 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; 323 324 return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 325 } 326 327 /* 328 * 'fdt_addr' is received as hwaddr because boards might put 329 * the FDT beyond 32-bit addressing boundary. 330 */ 331 void riscv_load_fdt(hwaddr fdt_addr, void *fdt) 332 { 333 uint32_t fdtsize = fdt_totalsize(fdt); 334 335 /* copy in the device tree */ 336 qemu_fdt_dumpdtb(fdt, fdtsize); 337 338 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 339 &address_space_memory); 340 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 341 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); 342 } 343 344 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 345 hwaddr rom_size, uint32_t reset_vec_size, 346 uint64_t kernel_entry) 347 { 348 struct fw_dynamic_info dinfo; 349 size_t dinfo_len; 350 351 if (sizeof(dinfo.magic) == 4) { 352 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 353 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 354 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 355 dinfo.next_addr = cpu_to_le32(kernel_entry); 356 } else { 357 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 358 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 359 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 360 dinfo.next_addr = cpu_to_le64(kernel_entry); 361 } 362 dinfo.options = 0; 363 dinfo.boot_hart = 0; 364 dinfo_len = sizeof(dinfo); 365 366 /** 367 * copy the dynamic firmware info. This information is specific to 368 * OpenSBI but doesn't break any other firmware as long as they don't 369 * expect any certain value in "a2" register. 370 */ 371 if (dinfo_len > (rom_size - reset_vec_size)) { 372 error_report("not enough space to store dynamic firmware info"); 373 exit(1); 374 } 375 376 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 377 rom_base + reset_vec_size, 378 &address_space_memory); 379 } 380 381 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 382 hwaddr start_addr, 383 hwaddr rom_base, hwaddr rom_size, 384 uint64_t kernel_entry, 385 uint64_t fdt_load_addr) 386 { 387 int i; 388 uint32_t start_addr_hi32 = 0x00000000; 389 uint32_t fdt_load_addr_hi32 = 0x00000000; 390 391 if (!riscv_is_32bit(harts)) { 392 start_addr_hi32 = start_addr >> 32; 393 fdt_load_addr_hi32 = fdt_load_addr >> 32; 394 } 395 /* reset vector */ 396 uint32_t reset_vec[10] = { 397 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 398 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 399 0xf1402573, /* csrr a0, mhartid */ 400 0, 401 0, 402 0x00028067, /* jr t0 */ 403 start_addr, /* start: .dword */ 404 start_addr_hi32, 405 fdt_load_addr, /* fdt_laddr: .dword */ 406 fdt_load_addr_hi32, 407 /* fw_dyn: */ 408 }; 409 if (riscv_is_32bit(harts)) { 410 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 411 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 412 } else { 413 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 414 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 415 } 416 417 if (!harts->harts[0].cfg.ext_icsr) { 418 /* 419 * The Zicsr extension has been disabled, so let's ensure we don't 420 * run the CSR instruction. Let's fill the address with a non 421 * compressed nop. 422 */ 423 reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ 424 } 425 426 /* copy in the reset vector in little_endian byte order */ 427 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 428 reset_vec[i] = cpu_to_le32(reset_vec[i]); 429 } 430 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 431 rom_base, &address_space_memory); 432 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), 433 kernel_entry); 434 } 435 436 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) 437 { 438 CPUState *cs; 439 440 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 441 RISCVCPU *riscv_cpu = RISCV_CPU(cs); 442 riscv_cpu->env.kernel_addr = kernel_addr; 443 riscv_cpu->env.fdt_addr = fdt_addr; 444 } 445 } 446 447 void riscv_setup_firmware_boot(MachineState *machine) 448 { 449 if (machine->kernel_filename) { 450 FWCfgState *fw_cfg; 451 fw_cfg = fw_cfg_find(); 452 453 assert(fw_cfg); 454 /* 455 * Expose the kernel, the command line, and the initrd in fw_cfg. 456 * We don't process them here at all, it's all left to the 457 * firmware. 458 */ 459 load_image_to_fw_cfg(fw_cfg, 460 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 461 machine->kernel_filename, 462 true); 463 load_image_to_fw_cfg(fw_cfg, 464 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 465 machine->initrd_filename, false); 466 467 if (machine->kernel_cmdline) { 468 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 469 strlen(machine->kernel_cmdline) + 1); 470 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 471 machine->kernel_cmdline); 472 } 473 } 474 } 475