1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/error-report.h" 25 #include "exec/cpu-defs.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/riscv/boot.h" 29 #include "hw/riscv/boot_opensbi.h" 30 #include "elf.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/qtest.h" 33 34 #include <libfdt.h> 35 36 bool riscv_is_32bit(RISCVHartArrayState *harts) 37 { 38 return harts->harts[0].env.misa_mxl_max == MXL_RV32; 39 } 40 41 /* 42 * Return the per-socket PLIC hart topology configuration string 43 * (caller must free with g_free()) 44 */ 45 char *riscv_plic_hart_config_string(int hart_count) 46 { 47 g_autofree const char **vals = g_new(const char *, hart_count + 1); 48 int i; 49 50 for (i = 0; i < hart_count; i++) { 51 CPUState *cs = qemu_get_cpu(i); 52 CPURISCVState *env = &RISCV_CPU(cs)->env; 53 54 if (riscv_has_ext(env, RVS)) { 55 vals[i] = "MS"; 56 } else { 57 vals[i] = "M"; 58 } 59 } 60 vals[i] = NULL; 61 62 /* g_strjoinv() obliges us to cast away const here */ 63 return g_strjoinv(",", (char **)vals); 64 } 65 66 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, 67 target_ulong firmware_end_addr) { 68 if (riscv_is_32bit(harts)) { 69 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 70 } else { 71 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 72 } 73 } 74 75 target_ulong riscv_find_and_load_firmware(MachineState *machine, 76 const char *default_machine_firmware, 77 hwaddr firmware_load_addr, 78 symbol_fn_t sym_cb) 79 { 80 char *firmware_filename = NULL; 81 target_ulong firmware_end_addr = firmware_load_addr; 82 83 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 84 /* 85 * The user didn't specify -bios, or has specified "-bios default". 86 * That means we are going to load the OpenSBI binary included in 87 * the QEMU source. 88 */ 89 firmware_filename = riscv_find_firmware(default_machine_firmware); 90 } else if (strcmp(machine->firmware, "none")) { 91 firmware_filename = riscv_find_firmware(machine->firmware); 92 } 93 94 if (firmware_filename) { 95 /* If not "none" load the firmware */ 96 firmware_end_addr = riscv_load_firmware(firmware_filename, 97 firmware_load_addr, sym_cb); 98 g_free(firmware_filename); 99 } 100 101 return firmware_end_addr; 102 } 103 104 char *riscv_find_firmware(const char *firmware_filename) 105 { 106 char *filename; 107 108 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 109 if (filename == NULL) { 110 if (!qtest_enabled()) { 111 /* 112 * We only ship plain binary bios images in the QEMU source. 113 * With Spike machine that uses ELF images as the default bios, 114 * running QEMU test will complain hence let's suppress the error 115 * report for QEMU testing. 116 */ 117 error_report("Unable to load the RISC-V firmware \"%s\"", 118 firmware_filename); 119 exit(1); 120 } 121 } 122 123 return filename; 124 } 125 126 target_ulong riscv_load_firmware(const char *firmware_filename, 127 hwaddr firmware_load_addr, 128 symbol_fn_t sym_cb) 129 { 130 uint64_t firmware_entry, firmware_size, firmware_end; 131 132 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 133 &firmware_entry, NULL, &firmware_end, NULL, 134 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 135 return firmware_end; 136 } 137 138 firmware_size = load_image_targphys_as(firmware_filename, 139 firmware_load_addr, 140 current_machine->ram_size, NULL); 141 142 if (firmware_size > 0) { 143 return firmware_load_addr + firmware_size; 144 } 145 146 error_report("could not load firmware '%s'", firmware_filename); 147 exit(1); 148 } 149 150 target_ulong riscv_load_kernel(const char *kernel_filename, 151 target_ulong kernel_start_addr, 152 symbol_fn_t sym_cb) 153 { 154 uint64_t kernel_load_base, kernel_entry; 155 156 /* 157 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 158 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 159 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 160 * the (expected) load address load address. This allows kernels to have 161 * separate SBI and ELF entry points (used by FreeBSD, for example). 162 */ 163 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 164 NULL, &kernel_load_base, NULL, NULL, 0, 165 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 166 return kernel_load_base; 167 } 168 169 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 170 NULL, NULL, NULL) > 0) { 171 return kernel_entry; 172 } 173 174 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 175 current_machine->ram_size, NULL) > 0) { 176 return kernel_start_addr; 177 } 178 179 error_report("could not load kernel '%s'", kernel_filename); 180 exit(1); 181 } 182 183 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 184 uint64_t kernel_entry, hwaddr *start) 185 { 186 int size; 187 188 /* 189 * We want to put the initrd far enough into RAM that when the 190 * kernel is uncompressed it will not clobber the initrd. However 191 * on boards without much RAM we must ensure that we still leave 192 * enough room for a decent sized initrd, and on boards with large 193 * amounts of RAM we must avoid the initrd being so far up in RAM 194 * that it is outside lowmem and inaccessible to the kernel. 195 * So for boards with less than 256MB of RAM we put the initrd 196 * halfway into RAM, and for boards with 256MB of RAM or more we put 197 * the initrd at 128MB. 198 */ 199 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 200 201 size = load_ramdisk(filename, *start, mem_size - *start); 202 if (size == -1) { 203 size = load_image_targphys(filename, *start, mem_size - *start); 204 if (size == -1) { 205 error_report("could not load ramdisk '%s'", filename); 206 exit(1); 207 } 208 } 209 210 return *start + size; 211 } 212 213 uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 214 { 215 uint32_t temp, fdt_addr; 216 hwaddr dram_end = dram_base + mem_size; 217 int ret, fdtsize = fdt_totalsize(fdt); 218 219 if (fdtsize <= 0) { 220 error_report("invalid device-tree"); 221 exit(1); 222 } 223 224 /* 225 * We should put fdt as far as possible to avoid kernel/initrd overwriting 226 * its content. But it should be addressable by 32 bit system as well. 227 * Thus, put it at an 16MB aligned address that less than fdt size from the 228 * end of dram or 3GB whichever is lesser. 229 */ 230 temp = MIN(dram_end, 3072 * MiB); 231 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB); 232 233 ret = fdt_pack(fdt); 234 /* Should only fail if we've built a corrupted tree */ 235 g_assert(ret == 0); 236 /* copy in the device tree */ 237 qemu_fdt_dumpdtb(fdt, fdtsize); 238 239 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 240 &address_space_memory); 241 242 return fdt_addr; 243 } 244 245 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 246 hwaddr rom_size, uint32_t reset_vec_size, 247 uint64_t kernel_entry) 248 { 249 struct fw_dynamic_info dinfo; 250 size_t dinfo_len; 251 252 if (sizeof(dinfo.magic) == 4) { 253 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 254 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 255 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 256 dinfo.next_addr = cpu_to_le32(kernel_entry); 257 } else { 258 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 259 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 260 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 261 dinfo.next_addr = cpu_to_le64(kernel_entry); 262 } 263 dinfo.options = 0; 264 dinfo.boot_hart = 0; 265 dinfo_len = sizeof(dinfo); 266 267 /** 268 * copy the dynamic firmware info. This information is specific to 269 * OpenSBI but doesn't break any other firmware as long as they don't 270 * expect any certain value in "a2" register. 271 */ 272 if (dinfo_len > (rom_size - reset_vec_size)) { 273 error_report("not enough space to store dynamic firmware info"); 274 exit(1); 275 } 276 277 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 278 rom_base + reset_vec_size, 279 &address_space_memory); 280 } 281 282 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 283 hwaddr start_addr, 284 hwaddr rom_base, hwaddr rom_size, 285 uint64_t kernel_entry, 286 uint32_t fdt_load_addr, void *fdt) 287 { 288 int i; 289 uint32_t start_addr_hi32 = 0x00000000; 290 291 if (!riscv_is_32bit(harts)) { 292 start_addr_hi32 = start_addr >> 32; 293 } 294 /* reset vector */ 295 uint32_t reset_vec[10] = { 296 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 297 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 298 0xf1402573, /* csrr a0, mhartid */ 299 0, 300 0, 301 0x00028067, /* jr t0 */ 302 start_addr, /* start: .dword */ 303 start_addr_hi32, 304 fdt_load_addr, /* fdt_laddr: .dword */ 305 0x00000000, 306 /* fw_dyn: */ 307 }; 308 if (riscv_is_32bit(harts)) { 309 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 310 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 311 } else { 312 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 313 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 314 } 315 316 /* copy in the reset vector in little_endian byte order */ 317 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 318 reset_vec[i] = cpu_to_le32(reset_vec[i]); 319 } 320 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 321 rom_base, &address_space_memory); 322 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), 323 kernel_entry); 324 325 return; 326 } 327