1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/qtest.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/reset.h" 34 35 #include <libfdt.h> 36 37 bool riscv_is_32bit(RISCVHartArrayState *harts) 38 { 39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); 40 return mcc->misa_mxl_max == MXL_RV32; 41 } 42 43 /* 44 * Return the per-socket PLIC hart topology configuration string 45 * (caller must free with g_free()) 46 */ 47 char *riscv_plic_hart_config_string(int hart_count) 48 { 49 g_autofree const char **vals = g_new(const char *, hart_count + 1); 50 int i; 51 52 for (i = 0; i < hart_count; i++) { 53 CPUState *cs = qemu_get_cpu(i); 54 CPURISCVState *env = &RISCV_CPU(cs)->env; 55 56 if (kvm_enabled()) { 57 vals[i] = "S"; 58 } else if (riscv_has_ext(env, RVS)) { 59 vals[i] = "MS"; 60 } else { 61 vals[i] = "M"; 62 } 63 } 64 vals[i] = NULL; 65 66 /* g_strjoinv() obliges us to cast away const here */ 67 return g_strjoinv(",", (char **)vals); 68 } 69 70 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) 71 { 72 info->kernel_size = 0; 73 info->is_32bit = riscv_is_32bit(harts); 74 } 75 76 target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, 77 target_ulong firmware_end_addr) { 78 if (info->is_32bit) { 79 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 80 } else { 81 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 82 } 83 } 84 85 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) 86 { 87 if (riscv_is_32bit(harts)) { 88 return RISCV32_BIOS_BIN; 89 } 90 91 return RISCV64_BIOS_BIN; 92 } 93 94 static char *riscv_find_bios(const char *bios_filename) 95 { 96 char *filename; 97 98 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); 99 if (filename == NULL) { 100 if (!qtest_enabled()) { 101 /* 102 * We only ship OpenSBI binary bios images in the QEMU source. 103 * For machines that use images other than the default bios, 104 * running QEMU test will complain hence let's suppress the error 105 * report for QEMU testing. 106 */ 107 error_report("Unable to find the RISC-V BIOS \"%s\"", 108 bios_filename); 109 exit(1); 110 } 111 } 112 113 return filename; 114 } 115 116 char *riscv_find_firmware(const char *firmware_filename, 117 const char *default_machine_firmware) 118 { 119 char *filename = NULL; 120 121 if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { 122 /* 123 * The user didn't specify -bios, or has specified "-bios default". 124 * That means we are going to load the OpenSBI binary included in 125 * the QEMU source. 126 */ 127 filename = riscv_find_bios(default_machine_firmware); 128 } else if (strcmp(firmware_filename, "none")) { 129 filename = riscv_find_bios(firmware_filename); 130 } 131 132 return filename; 133 } 134 135 target_ulong riscv_find_and_load_firmware(MachineState *machine, 136 const char *default_machine_firmware, 137 hwaddr *firmware_load_addr, 138 symbol_fn_t sym_cb) 139 { 140 char *firmware_filename; 141 target_ulong firmware_end_addr = *firmware_load_addr; 142 143 firmware_filename = riscv_find_firmware(machine->firmware, 144 default_machine_firmware); 145 146 if (firmware_filename) { 147 /* If not "none" load the firmware */ 148 firmware_end_addr = riscv_load_firmware(firmware_filename, 149 firmware_load_addr, sym_cb); 150 g_free(firmware_filename); 151 } 152 153 return firmware_end_addr; 154 } 155 156 target_ulong riscv_load_firmware(const char *firmware_filename, 157 hwaddr *firmware_load_addr, 158 symbol_fn_t sym_cb) 159 { 160 uint64_t firmware_entry, firmware_end; 161 ssize_t firmware_size; 162 163 g_assert(firmware_filename != NULL); 164 165 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 166 &firmware_entry, NULL, &firmware_end, NULL, 167 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 168 *firmware_load_addr = firmware_entry; 169 return firmware_end; 170 } 171 172 firmware_size = load_image_targphys_as(firmware_filename, 173 *firmware_load_addr, 174 current_machine->ram_size, NULL); 175 176 if (firmware_size > 0) { 177 return *firmware_load_addr + firmware_size; 178 } 179 180 error_report("could not load firmware '%s'", firmware_filename); 181 exit(1); 182 } 183 184 static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) 185 { 186 const char *filename = machine->initrd_filename; 187 uint64_t mem_size = machine->ram_size; 188 void *fdt = machine->fdt; 189 hwaddr start, end; 190 ssize_t size; 191 192 g_assert(filename != NULL); 193 194 /* 195 * We want to put the initrd far enough into RAM that when the 196 * kernel is uncompressed it will not clobber the initrd. However 197 * on boards without much RAM we must ensure that we still leave 198 * enough room for a decent sized initrd, and on boards with large 199 * amounts of RAM, we put the initrd at 512MB to allow large kernels 200 * to boot. 201 * So for boards with less than 1GB of RAM we put the initrd 202 * halfway into RAM, and for boards with 1GB of RAM or more we put 203 * the initrd at 512MB. 204 */ 205 start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB); 206 207 size = load_ramdisk(filename, start, mem_size - start); 208 if (size == -1) { 209 size = load_image_targphys(filename, start, mem_size - start); 210 if (size == -1) { 211 error_report("could not load ramdisk '%s'", filename); 212 exit(1); 213 } 214 } 215 216 /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ 217 if (fdt) { 218 end = start + size; 219 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start); 220 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end); 221 } 222 } 223 224 void riscv_load_kernel(MachineState *machine, 225 RISCVBootInfo *info, 226 target_ulong kernel_start_addr, 227 bool load_initrd, 228 symbol_fn_t sym_cb) 229 { 230 const char *kernel_filename = machine->kernel_filename; 231 ssize_t kernel_size; 232 void *fdt = machine->fdt; 233 234 g_assert(kernel_filename != NULL); 235 236 /* 237 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 238 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 239 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 240 * the (expected) load address load address. This allows kernels to have 241 * separate SBI and ELF entry points (used by FreeBSD, for example). 242 */ 243 kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, 244 &info->image_low_addr, &info->image_high_addr, 245 NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb); 246 if (kernel_size > 0) { 247 info->kernel_size = kernel_size; 248 goto out; 249 } 250 251 kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr, 252 NULL, NULL, NULL, NULL, NULL); 253 if (kernel_size > 0) { 254 info->kernel_size = kernel_size; 255 info->image_high_addr = info->image_low_addr + kernel_size; 256 goto out; 257 } 258 259 kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr, 260 current_machine->ram_size, NULL); 261 if (kernel_size > 0) { 262 info->kernel_size = kernel_size; 263 info->image_low_addr = kernel_start_addr; 264 info->image_high_addr = info->image_low_addr + kernel_size; 265 goto out; 266 } 267 268 error_report("could not load kernel '%s'", kernel_filename); 269 exit(1); 270 271 out: 272 /* 273 * For 32 bit CPUs 'image_low_addr' can be sign-extended by 274 * load_elf_ram_sym(). 275 */ 276 if (info->is_32bit) { 277 info->image_low_addr = extract64(info->image_low_addr, 0, 32); 278 } 279 280 if (load_initrd && machine->initrd_filename) { 281 riscv_load_initrd(machine, info); 282 } 283 284 if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { 285 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 286 machine->kernel_cmdline); 287 } 288 } 289 290 /* 291 * This function makes an assumption that the DRAM interval 292 * 'dram_base' + 'dram_size' is contiguous. 293 * 294 * Considering that 'dram_end' is the lowest value between 295 * the end of the DRAM block and MachineState->ram_size, the 296 * FDT location will vary according to 'dram_base': 297 * 298 * - if 'dram_base' is less that 3072 MiB, the FDT will be 299 * put at the lowest value between 3072 MiB and 'dram_end'; 300 * 301 * - if 'dram_base' is higher than 3072 MiB, the FDT will be 302 * put at 'dram_end'. 303 * 304 * The FDT is fdt_packed() during the calculation. 305 */ 306 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, 307 MachineState *ms, RISCVBootInfo *info) 308 { 309 int ret = fdt_pack(ms->fdt); 310 hwaddr dram_end, temp; 311 int fdtsize; 312 313 /* Should only fail if we've built a corrupted tree */ 314 g_assert(ret == 0); 315 316 fdtsize = fdt_totalsize(ms->fdt); 317 if (fdtsize <= 0) { 318 error_report("invalid device-tree"); 319 exit(1); 320 } 321 322 /* 323 * A dram_size == 0, usually from a MemMapEntry[].size element, 324 * means that the DRAM block goes all the way to ms->ram_size. 325 */ 326 dram_end = dram_base; 327 dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size; 328 329 /* 330 * We should put fdt as far as possible to avoid kernel/initrd overwriting 331 * its content. But it should be addressable by 32 bit system as well in RV32. 332 * Thus, put it near to the end of dram in RV64, and put it near to the end 333 * of dram or 3GB whichever is lesser in RV32. 334 */ 335 if (!info->is_32bit) { 336 temp = dram_end; 337 } else { 338 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; 339 } 340 341 return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 342 } 343 344 /* 345 * 'fdt_addr' is received as hwaddr because boards might put 346 * the FDT beyond 32-bit addressing boundary. 347 */ 348 void riscv_load_fdt(hwaddr fdt_addr, void *fdt) 349 { 350 uint32_t fdtsize = fdt_totalsize(fdt); 351 352 /* copy in the device tree */ 353 qemu_fdt_dumpdtb(fdt, fdtsize); 354 355 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 356 &address_space_memory); 357 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 358 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); 359 } 360 361 void riscv_rom_copy_firmware_info(MachineState *machine, 362 RISCVHartArrayState *harts, 363 hwaddr rom_base, hwaddr rom_size, 364 uint32_t reset_vec_size, 365 uint64_t kernel_entry) 366 { 367 struct fw_dynamic_info32 dinfo32; 368 struct fw_dynamic_info dinfo; 369 size_t dinfo_len; 370 371 if (riscv_is_32bit(harts)) { 372 dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 373 dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 374 dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 375 dinfo32.next_addr = cpu_to_le32(kernel_entry); 376 dinfo32.options = 0; 377 dinfo32.boot_hart = 0; 378 dinfo_len = sizeof(dinfo32); 379 } else { 380 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 381 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 382 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 383 dinfo.next_addr = cpu_to_le64(kernel_entry); 384 dinfo.options = 0; 385 dinfo.boot_hart = 0; 386 dinfo_len = sizeof(dinfo); 387 } 388 389 /** 390 * copy the dynamic firmware info. This information is specific to 391 * OpenSBI but doesn't break any other firmware as long as they don't 392 * expect any certain value in "a2" register. 393 */ 394 if (dinfo_len > (rom_size - reset_vec_size)) { 395 error_report("not enough space to store dynamic firmware info"); 396 exit(1); 397 } 398 399 rom_add_blob_fixed_as("mrom.finfo", 400 riscv_is_32bit(harts) ? 401 (void *)&dinfo32 : (void *)&dinfo, 402 dinfo_len, 403 rom_base + reset_vec_size, 404 &address_space_memory); 405 } 406 407 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 408 hwaddr start_addr, 409 hwaddr rom_base, hwaddr rom_size, 410 uint64_t kernel_entry, 411 uint64_t fdt_load_addr) 412 { 413 int i; 414 uint32_t start_addr_hi32 = 0x00000000; 415 uint32_t fdt_load_addr_hi32 = 0x00000000; 416 417 if (!riscv_is_32bit(harts)) { 418 start_addr_hi32 = start_addr >> 32; 419 fdt_load_addr_hi32 = fdt_load_addr >> 32; 420 } 421 /* reset vector */ 422 uint32_t reset_vec[10] = { 423 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 424 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 425 0xf1402573, /* csrr a0, mhartid */ 426 0, 427 0, 428 0x00028067, /* jr t0 */ 429 start_addr, /* start: .dword */ 430 start_addr_hi32, 431 fdt_load_addr, /* fdt_laddr: .dword */ 432 fdt_load_addr_hi32, 433 /* fw_dyn: */ 434 }; 435 if (riscv_is_32bit(harts)) { 436 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 437 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 438 } else { 439 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 440 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 441 } 442 443 if (!harts->harts[0].cfg.ext_zicsr) { 444 /* 445 * The Zicsr extension has been disabled, so let's ensure we don't 446 * run the CSR instruction. Let's fill the address with a non 447 * compressed nop. 448 */ 449 reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ 450 } 451 452 /* copy in the reset vector in little_endian byte order */ 453 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 454 reset_vec[i] = cpu_to_le32(reset_vec[i]); 455 } 456 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 457 rom_base, &address_space_memory); 458 riscv_rom_copy_firmware_info(machine, harts, 459 rom_base, rom_size, 460 sizeof(reset_vec), 461 kernel_entry); 462 } 463 464 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) 465 { 466 CPUState *cs; 467 468 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 469 RISCVCPU *riscv_cpu = RISCV_CPU(cs); 470 riscv_cpu->env.kernel_addr = kernel_addr; 471 riscv_cpu->env.fdt_addr = fdt_addr; 472 } 473 } 474 475 void riscv_setup_firmware_boot(MachineState *machine) 476 { 477 if (machine->kernel_filename) { 478 FWCfgState *fw_cfg; 479 fw_cfg = fw_cfg_find(); 480 481 assert(fw_cfg); 482 /* 483 * Expose the kernel, the command line, and the initrd in fw_cfg. 484 * We don't process them here at all, it's all left to the 485 * firmware. 486 */ 487 load_image_to_fw_cfg(fw_cfg, 488 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 489 machine->kernel_filename, 490 true); 491 load_image_to_fw_cfg(fw_cfg, 492 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 493 machine->initrd_filename, false); 494 495 if (machine->kernel_cmdline) { 496 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 497 strlen(machine->kernel_cmdline) + 1); 498 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 499 machine->kernel_cmdline); 500 } 501 } 502 } 503