1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/qtest.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/reset.h" 34 35 #include <libfdt.h> 36 37 bool riscv_is_32bit(RISCVHartArrayState *harts) 38 { 39 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); 40 return mcc->misa_mxl_max == MXL_RV32; 41 } 42 43 /* 44 * Return the per-socket PLIC hart topology configuration string 45 * (caller must free with g_free()) 46 */ 47 char *riscv_plic_hart_config_string(int hart_count) 48 { 49 g_autofree const char **vals = g_new(const char *, hart_count + 1); 50 int i; 51 52 for (i = 0; i < hart_count; i++) { 53 CPUState *cs = qemu_get_cpu(i); 54 CPURISCVState *env = &RISCV_CPU(cs)->env; 55 56 if (kvm_enabled()) { 57 vals[i] = "S"; 58 } else if (riscv_has_ext(env, RVS)) { 59 vals[i] = "MS"; 60 } else { 61 vals[i] = "M"; 62 } 63 } 64 vals[i] = NULL; 65 66 /* g_strjoinv() obliges us to cast away const here */ 67 return g_strjoinv(",", (char **)vals); 68 } 69 70 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, 71 target_ulong firmware_end_addr) { 72 if (riscv_is_32bit(harts)) { 73 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 74 } else { 75 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 76 } 77 } 78 79 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) 80 { 81 if (riscv_is_32bit(harts)) { 82 return RISCV32_BIOS_BIN; 83 } 84 85 return RISCV64_BIOS_BIN; 86 } 87 88 static char *riscv_find_bios(const char *bios_filename) 89 { 90 char *filename; 91 92 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); 93 if (filename == NULL) { 94 if (!qtest_enabled()) { 95 /* 96 * We only ship OpenSBI binary bios images in the QEMU source. 97 * For machines that use images other than the default bios, 98 * running QEMU test will complain hence let's suppress the error 99 * report for QEMU testing. 100 */ 101 error_report("Unable to find the RISC-V BIOS \"%s\"", 102 bios_filename); 103 exit(1); 104 } 105 } 106 107 return filename; 108 } 109 110 char *riscv_find_firmware(const char *firmware_filename, 111 const char *default_machine_firmware) 112 { 113 char *filename = NULL; 114 115 if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { 116 /* 117 * The user didn't specify -bios, or has specified "-bios default". 118 * That means we are going to load the OpenSBI binary included in 119 * the QEMU source. 120 */ 121 filename = riscv_find_bios(default_machine_firmware); 122 } else if (strcmp(firmware_filename, "none")) { 123 filename = riscv_find_bios(firmware_filename); 124 } 125 126 return filename; 127 } 128 129 target_ulong riscv_find_and_load_firmware(MachineState *machine, 130 const char *default_machine_firmware, 131 hwaddr *firmware_load_addr, 132 symbol_fn_t sym_cb) 133 { 134 char *firmware_filename; 135 target_ulong firmware_end_addr = *firmware_load_addr; 136 137 firmware_filename = riscv_find_firmware(machine->firmware, 138 default_machine_firmware); 139 140 if (firmware_filename) { 141 /* If not "none" load the firmware */ 142 firmware_end_addr = riscv_load_firmware(firmware_filename, 143 firmware_load_addr, sym_cb); 144 g_free(firmware_filename); 145 } 146 147 return firmware_end_addr; 148 } 149 150 target_ulong riscv_load_firmware(const char *firmware_filename, 151 hwaddr *firmware_load_addr, 152 symbol_fn_t sym_cb) 153 { 154 uint64_t firmware_entry, firmware_end; 155 ssize_t firmware_size; 156 157 g_assert(firmware_filename != NULL); 158 159 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 160 &firmware_entry, NULL, &firmware_end, NULL, 161 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 162 *firmware_load_addr = firmware_entry; 163 return firmware_end; 164 } 165 166 firmware_size = load_image_targphys_as(firmware_filename, 167 *firmware_load_addr, 168 current_machine->ram_size, NULL); 169 170 if (firmware_size > 0) { 171 return *firmware_load_addr + firmware_size; 172 } 173 174 error_report("could not load firmware '%s'", firmware_filename); 175 exit(1); 176 } 177 178 static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) 179 { 180 const char *filename = machine->initrd_filename; 181 uint64_t mem_size = machine->ram_size; 182 void *fdt = machine->fdt; 183 hwaddr start, end; 184 ssize_t size; 185 186 g_assert(filename != NULL); 187 188 /* 189 * We want to put the initrd far enough into RAM that when the 190 * kernel is uncompressed it will not clobber the initrd. However 191 * on boards without much RAM we must ensure that we still leave 192 * enough room for a decent sized initrd, and on boards with large 193 * amounts of RAM, we put the initrd at 512MB to allow large kernels 194 * to boot. 195 * So for boards with less than 1GB of RAM we put the initrd 196 * halfway into RAM, and for boards with 1GB of RAM or more we put 197 * the initrd at 512MB. 198 */ 199 start = kernel_entry + MIN(mem_size / 2, 512 * MiB); 200 201 size = load_ramdisk(filename, start, mem_size - start); 202 if (size == -1) { 203 size = load_image_targphys(filename, start, mem_size - start); 204 if (size == -1) { 205 error_report("could not load ramdisk '%s'", filename); 206 exit(1); 207 } 208 } 209 210 /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ 211 if (fdt) { 212 end = start + size; 213 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start); 214 qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end); 215 } 216 } 217 218 target_ulong riscv_load_kernel(MachineState *machine, 219 RISCVHartArrayState *harts, 220 target_ulong kernel_start_addr, 221 bool load_initrd, 222 symbol_fn_t sym_cb) 223 { 224 const char *kernel_filename = machine->kernel_filename; 225 uint64_t kernel_load_base, kernel_entry; 226 void *fdt = machine->fdt; 227 228 g_assert(kernel_filename != NULL); 229 230 /* 231 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 232 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 233 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 234 * the (expected) load address load address. This allows kernels to have 235 * separate SBI and ELF entry points (used by FreeBSD, for example). 236 */ 237 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 238 NULL, &kernel_load_base, NULL, NULL, 0, 239 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 240 kernel_entry = kernel_load_base; 241 goto out; 242 } 243 244 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 245 NULL, NULL, NULL) > 0) { 246 goto out; 247 } 248 249 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 250 current_machine->ram_size, NULL) > 0) { 251 kernel_entry = kernel_start_addr; 252 goto out; 253 } 254 255 error_report("could not load kernel '%s'", kernel_filename); 256 exit(1); 257 258 out: 259 /* 260 * For 32 bit CPUs 'kernel_entry' can be sign-extended by 261 * load_elf_ram_sym(). 262 */ 263 if (riscv_is_32bit(harts)) { 264 kernel_entry = extract64(kernel_entry, 0, 32); 265 } 266 267 if (load_initrd && machine->initrd_filename) { 268 riscv_load_initrd(machine, kernel_entry); 269 } 270 271 if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { 272 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 273 machine->kernel_cmdline); 274 } 275 276 return kernel_entry; 277 } 278 279 /* 280 * This function makes an assumption that the DRAM interval 281 * 'dram_base' + 'dram_size' is contiguous. 282 * 283 * Considering that 'dram_end' is the lowest value between 284 * the end of the DRAM block and MachineState->ram_size, the 285 * FDT location will vary according to 'dram_base': 286 * 287 * - if 'dram_base' is less that 3072 MiB, the FDT will be 288 * put at the lowest value between 3072 MiB and 'dram_end'; 289 * 290 * - if 'dram_base' is higher than 3072 MiB, the FDT will be 291 * put at 'dram_end'. 292 * 293 * The FDT is fdt_packed() during the calculation. 294 */ 295 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, 296 MachineState *ms) 297 { 298 int ret = fdt_pack(ms->fdt); 299 hwaddr dram_end, temp; 300 int fdtsize; 301 302 /* Should only fail if we've built a corrupted tree */ 303 g_assert(ret == 0); 304 305 fdtsize = fdt_totalsize(ms->fdt); 306 if (fdtsize <= 0) { 307 error_report("invalid device-tree"); 308 exit(1); 309 } 310 311 /* 312 * A dram_size == 0, usually from a MemMapEntry[].size element, 313 * means that the DRAM block goes all the way to ms->ram_size. 314 */ 315 dram_end = dram_base; 316 dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size; 317 318 /* 319 * We should put fdt as far as possible to avoid kernel/initrd overwriting 320 * its content. But it should be addressable by 32 bit system as well. 321 * Thus, put it at an 2MB aligned address that less than fdt size from the 322 * end of dram or 3GB whichever is lesser. 323 */ 324 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; 325 326 return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 327 } 328 329 /* 330 * 'fdt_addr' is received as hwaddr because boards might put 331 * the FDT beyond 32-bit addressing boundary. 332 */ 333 void riscv_load_fdt(hwaddr fdt_addr, void *fdt) 334 { 335 uint32_t fdtsize = fdt_totalsize(fdt); 336 337 /* copy in the device tree */ 338 qemu_fdt_dumpdtb(fdt, fdtsize); 339 340 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 341 &address_space_memory); 342 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 343 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); 344 } 345 346 void riscv_rom_copy_firmware_info(MachineState *machine, 347 RISCVHartArrayState *harts, 348 hwaddr rom_base, hwaddr rom_size, 349 uint32_t reset_vec_size, 350 uint64_t kernel_entry) 351 { 352 struct fw_dynamic_info32 dinfo32; 353 struct fw_dynamic_info dinfo; 354 size_t dinfo_len; 355 356 if (riscv_is_32bit(harts)) { 357 dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 358 dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 359 dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 360 dinfo32.next_addr = cpu_to_le32(kernel_entry); 361 dinfo32.options = 0; 362 dinfo32.boot_hart = 0; 363 dinfo_len = sizeof(dinfo32); 364 } else { 365 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 366 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 367 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 368 dinfo.next_addr = cpu_to_le64(kernel_entry); 369 dinfo.options = 0; 370 dinfo.boot_hart = 0; 371 dinfo_len = sizeof(dinfo); 372 } 373 374 /** 375 * copy the dynamic firmware info. This information is specific to 376 * OpenSBI but doesn't break any other firmware as long as they don't 377 * expect any certain value in "a2" register. 378 */ 379 if (dinfo_len > (rom_size - reset_vec_size)) { 380 error_report("not enough space to store dynamic firmware info"); 381 exit(1); 382 } 383 384 rom_add_blob_fixed_as("mrom.finfo", 385 riscv_is_32bit(harts) ? 386 (void *)&dinfo32 : (void *)&dinfo, 387 dinfo_len, 388 rom_base + reset_vec_size, 389 &address_space_memory); 390 } 391 392 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 393 hwaddr start_addr, 394 hwaddr rom_base, hwaddr rom_size, 395 uint64_t kernel_entry, 396 uint64_t fdt_load_addr) 397 { 398 int i; 399 uint32_t start_addr_hi32 = 0x00000000; 400 uint32_t fdt_load_addr_hi32 = 0x00000000; 401 402 if (!riscv_is_32bit(harts)) { 403 start_addr_hi32 = start_addr >> 32; 404 fdt_load_addr_hi32 = fdt_load_addr >> 32; 405 } 406 /* reset vector */ 407 uint32_t reset_vec[10] = { 408 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 409 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 410 0xf1402573, /* csrr a0, mhartid */ 411 0, 412 0, 413 0x00028067, /* jr t0 */ 414 start_addr, /* start: .dword */ 415 start_addr_hi32, 416 fdt_load_addr, /* fdt_laddr: .dword */ 417 fdt_load_addr_hi32, 418 /* fw_dyn: */ 419 }; 420 if (riscv_is_32bit(harts)) { 421 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 422 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 423 } else { 424 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 425 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 426 } 427 428 if (!harts->harts[0].cfg.ext_zicsr) { 429 /* 430 * The Zicsr extension has been disabled, so let's ensure we don't 431 * run the CSR instruction. Let's fill the address with a non 432 * compressed nop. 433 */ 434 reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ 435 } 436 437 /* copy in the reset vector in little_endian byte order */ 438 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 439 reset_vec[i] = cpu_to_le32(reset_vec[i]); 440 } 441 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 442 rom_base, &address_space_memory); 443 riscv_rom_copy_firmware_info(machine, harts, 444 rom_base, rom_size, 445 sizeof(reset_vec), 446 kernel_entry); 447 } 448 449 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) 450 { 451 CPUState *cs; 452 453 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 454 RISCVCPU *riscv_cpu = RISCV_CPU(cs); 455 riscv_cpu->env.kernel_addr = kernel_addr; 456 riscv_cpu->env.fdt_addr = fdt_addr; 457 } 458 } 459 460 void riscv_setup_firmware_boot(MachineState *machine) 461 { 462 if (machine->kernel_filename) { 463 FWCfgState *fw_cfg; 464 fw_cfg = fw_cfg_find(); 465 466 assert(fw_cfg); 467 /* 468 * Expose the kernel, the command line, and the initrd in fw_cfg. 469 * We don't process them here at all, it's all left to the 470 * firmware. 471 */ 472 load_image_to_fw_cfg(fw_cfg, 473 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 474 machine->kernel_filename, 475 true); 476 load_image_to_fw_cfg(fw_cfg, 477 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 478 machine->initrd_filename, false); 479 480 if (machine->kernel_cmdline) { 481 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 482 strlen(machine->kernel_cmdline) + 1); 483 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 484 machine->kernel_cmdline); 485 } 486 } 487 } 488